diff --git a/0001-Add-loongarch64-support-for-rust-1.57.patch b/0001-Add-loongarch64-support-for-rust-1.57.patch new file mode 100644 index 0000000000000000000000000000000000000000..be9582ac0f80dd13381b6a71026d63dce1e1291f --- /dev/null +++ b/0001-Add-loongarch64-support-for-rust-1.57.patch @@ -0,0 +1,1784 @@ +From a4bd2d073172884158b83c743055855657312d52 Mon Sep 17 00:00:00 2001 +From: yangxiaojuan +Date: Mon, 22 Aug 2022 20:30:26 +0800 +Subject: [PATCH 1/2] Add loongarch64 support for rust-1.57 + +Change-Id: I085b3955edcb15c6f8d42b585ba966233652e675 +--- + .../example/alloc_system.rs | 1 + + .../rustc_codegen_cranelift/src/metadata.rs | 1 + + .../rustc_codegen_gcc/example/alloc_system.rs | 1 + + compiler/rustc_codegen_gcc/src/asm.rs | 5 + + compiler/rustc_codegen_llvm/src/asm.rs | 6 + + compiler/rustc_codegen_ssa/src/back/link.rs | 7 + + .../rustc_codegen_ssa/src/target_features.rs | 7 + + compiler/rustc_feature/src/active.rs | 1 + + compiler/rustc_llvm/build.rs | 1 + + .../rustc_llvm/llvm-wrapper/PassWrapper.cpp | 7 + + compiler/rustc_llvm/src/lib.rs | 8 + + compiler/rustc_span/src/symbol.rs | 1 + + .../rustc_target/src/abi/call/loongarch.rs | 343 ++++++++++++++++++ + compiler/rustc_target/src/abi/call/mod.rs | 2 + + compiler/rustc_target/src/asm/loongarch.rs | 130 +++++++ + compiler/rustc_target/src/asm/mod.rs | 25 ++ + .../spec/loongarch64_unknown_linux_gnuf64.rs | 19 + + compiler/rustc_target/src/spec/mod.rs | 1 + + compiler/rustc_typeck/src/collect.rs | 1 + + library/core/src/lib.rs | 1 + + library/panic_unwind/src/gcc.rs | 3 + + library/std/src/env.rs | 1 + + library/std/src/os/linux/raw.rs | 1 + + library/std/src/sys/common/alloc.rs | 1 + + library/unwind/src/libunwind.rs | 3 + + src/bootstrap/bootstrap.py | 1 + + src/bootstrap/native.rs | 2 +- + src/ci/github-actions/ci.yml | 3 + + src/doc/rustc/src/platform-support.md | 1 + + src/librustdoc/clean/cfg.rs | 1 + + src/test/assembly/asm/loongarch-types.rs | 194 ++++++++++ + .../codegen/abi-main-signature-16bit-c-int.rs | 1 + + src/test/codegen/call-llvm-intrinsics.rs | 1 + + src/test/codegen/fastcall-inreg.rs | 1 + + src/test/codegen/global_asm.rs | 1 + + src/test/codegen/global_asm_include.rs | 1 + + src/test/codegen/global_asm_x2.rs | 1 + + .../loongarch-abi/call-llvm-intrinsics.rs | 30 ++ + .../codegen/repr-transparent-aggregates-1.rs | 1 + + .../codegen/repr-transparent-aggregates-2.rs | 1 + + src/test/codegen/repr-transparent.rs | 1 + + src/test/codegen/stack-probes.rs | 1 + + .../atomic-lock-free/Makefile | 4 + + src/test/ui/abi/stack-probes-lto.rs | 1 + + src/test/ui/borrowck/borrowck-asm.rs | 2 + + src/test/ui/cfg/conditional-compile-arch.rs | 3 + + src/test/ui/empty_global_asm.rs | 3 + + src/test/ui/llvm-asm/llvm-asm-bad-clobber.rs | 1 + + .../ui/llvm-asm/llvm-asm-in-bad-modifier.rs | 1 + + .../ui/llvm-asm/llvm-asm-misplaced-option.rs | 1 + + .../ui/llvm-asm/llvm-asm-out-assign-imm.rs | 1 + + .../ui/llvm-asm/llvm-asm-out-no-modifier.rs | 1 + + .../ui/llvm-asm/llvm-asm-out-read-uninit.rs | 1 + + src/test/ui/target-feature/gate.rs | 2 + + .../ui/target-feature/invalid-attribute.rs | 1 + + src/tools/build-manifest/src/main.rs | 2 + + src/tools/clippy/tests/ui/asm_syntax.rs | 1 + + src/tools/compiletest/src/json.rs | 4 +- + src/tools/compiletest/src/util.rs | 3 +- + src/tools/miri/src/shims/foreign_items.rs | 2 +- + 60 files changed, 848 insertions(+), 5 deletions(-) + create mode 100644 compiler/rustc_target/src/abi/call/loongarch.rs + create mode 100644 compiler/rustc_target/src/asm/loongarch.rs + create mode 100644 compiler/rustc_target/src/spec/loongarch64_unknown_linux_gnuf64.rs + create mode 100644 src/test/assembly/asm/loongarch-types.rs + create mode 100644 src/test/codegen/loongarch-abi/call-llvm-intrinsics.rs + +diff --git a/compiler/rustc_codegen_cranelift/example/alloc_system.rs b/compiler/rustc_codegen_cranelift/example/alloc_system.rs +index 5f66ca67f..c11979acd 100644 +--- a/compiler/rustc_codegen_cranelift/example/alloc_system.rs ++++ b/compiler/rustc_codegen_cranelift/example/alloc_system.rs +@@ -21,6 +21,7 @@ + const MIN_ALIGN: usize = 8; + #[cfg(all(any(target_arch = "x86_64", + target_arch = "aarch64", ++ target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "s390x", + target_arch = "sparc64")))] +diff --git a/compiler/rustc_codegen_cranelift/src/metadata.rs b/compiler/rustc_codegen_cranelift/src/metadata.rs +index 1c8fd0b01..c06876ad2 100644 +--- a/compiler/rustc_codegen_cranelift/src/metadata.rs ++++ b/compiler/rustc_codegen_cranelift/src/metadata.rs +@@ -31,6 +31,7 @@ pub(crate) fn new_metadata_object( + target_lexicon::Architecture::Arm(_) => object::Architecture::Arm, + target_lexicon::Architecture::Avr => object::Architecture::Avr, + target_lexicon::Architecture::Hexagon => object::Architecture::Hexagon, ++ target_lexicon::Architecture::LoongArch64(_) => object::Architecture::LoongArch64, + target_lexicon::Architecture::Mips32(_) => object::Architecture::Mips, + target_lexicon::Architecture::Mips64(_) => object::Architecture::Mips64, + target_lexicon::Architecture::Msp430 => object::Architecture::Msp430, +diff --git a/compiler/rustc_codegen_gcc/example/alloc_system.rs b/compiler/rustc_codegen_gcc/example/alloc_system.rs +index 5f66ca67f..c11979acd 100644 +--- a/compiler/rustc_codegen_gcc/example/alloc_system.rs ++++ b/compiler/rustc_codegen_gcc/example/alloc_system.rs +@@ -21,6 +21,7 @@ + const MIN_ALIGN: usize = 8; + #[cfg(all(any(target_arch = "x86_64", + target_arch = "aarch64", ++ target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "s390x", + target_arch = "sparc64")))] +diff --git a/compiler/rustc_codegen_gcc/src/asm.rs b/compiler/rustc_codegen_gcc/src/asm.rs +index 3b77097e9..6016ca480 100644 +--- a/compiler/rustc_codegen_gcc/src/asm.rs ++++ b/compiler/rustc_codegen_gcc/src/asm.rs +@@ -572,6 +572,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { + | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(), + InlineAsmRegClass::Bpf(_) => unimplemented!(), + InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(), ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => unimplemented!(), ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => unimplemented!(), + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(), + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => unimplemented!(), + InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => unimplemented!(), +@@ -634,6 +636,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl + } + InlineAsmRegClass::Bpf(_) => unimplemented!(), + InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(), ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(), ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(), + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(), + InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(), + InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(), +@@ -742,6 +746,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option + } + InlineAsmRegClass::Bpf(_) => unimplemented!(), + InlineAsmRegClass::Hexagon(_) => unimplemented!(), ++ InlineAsmRegClass::LoongArch(_) => unimplemented!(), + InlineAsmRegClass::Mips(_) => unimplemented!(), + InlineAsmRegClass::Nvptx(_) => unimplemented!(), + InlineAsmRegClass::PowerPC(_) => unimplemented!(), +diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs +index 341a88824..95db9af9d 100644 +--- a/compiler/rustc_codegen_llvm/src/asm.rs ++++ b/compiler/rustc_codegen_llvm/src/asm.rs +@@ -318,6 +318,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> { + InlineAsmArch::SpirV => {} + InlineAsmArch::Wasm32 => {} + InlineAsmArch::Bpf => {} ++ InlineAsmArch::LoongArch64 => {} + } + } + if !options.contains(InlineAsmOptions::NOMEM) { +@@ -643,6 +644,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => "r", ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => "f", + InlineAsmRegClass::Err => unreachable!(), + } + .to_string(), +@@ -722,6 +725,7 @@ fn modifier_to_llvm( + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } ++ InlineAsmRegClass::LoongArch(_) => None, + InlineAsmRegClass::Err => unreachable!(), + } + } +@@ -786,6 +790,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll + InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { + bug!("LLVM backend does not support SPIR-V") + } ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(), ++ InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(), + InlineAsmRegClass::Err => unreachable!(), + } + } +diff --git a/compiler/rustc_codegen_ssa/src/back/link.rs b/compiler/rustc_codegen_ssa/src/back/link.rs +index cf1c60588..535689158 100644 +--- a/compiler/rustc_codegen_ssa/src/back/link.rs ++++ b/compiler/rustc_codegen_ssa/src/back/link.rs +@@ -392,6 +392,7 @@ fn link_rlib<'a, B: ArchiveBuilder<'a>>( + "aarch64" => Architecture::Aarch64, + "x86" => Architecture::I386, + "s390x" => Architecture::S390x, ++ "loongarch64" => Architecture::LoongArch64, + "mips" => Architecture::Mips, + "mips64" => Architecture::Mips64, + "x86_64" => { +@@ -447,6 +448,12 @@ fn link_rlib<'a, B: ArchiveBuilder<'a>>( + let mut file = Object::new(BinaryFormat::Elf, architecture, endianness); + + match &sess.target.arch[..] { ++ // copied from `loongarch64-linux-gnu-gcc foo.c -c` ++ "loongarch64" => { ++ let e_flags = elf::EF_LARCH_ABI_LP64D; ++ file.flags = FileFlags::Elf { e_flags }; ++ } ++ + // copied from `mipsel-linux-gnu-gcc foo.c -c` and + // inspecting the resulting `e_flags` field. + "mips" => { +diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs +index 8d7e9612f..1bd2ea2f6 100644 +--- a/compiler/rustc_codegen_ssa/src/target_features.rs ++++ b/compiler/rustc_codegen_ssa/src/target_features.rs +@@ -181,6 +181,11 @@ const HEXAGON_ALLOWED_FEATURES: &[(&str, Option)] = &[ + ("hvx-length128b", Some(sym::hexagon_target_feature)), + ]; + ++const LOONGARCH64_ALLOWED_FEATURES: &[(&str, Option)] =&[ ++ ("d", Some(sym::loongarch64_target_feature)), ++ ("f", Some(sym::loongarch64_target_feature)), ++]; ++ + const POWERPC_ALLOWED_FEATURES: &[(&str, Option)] = &[ + ("altivec", Some(sym::powerpc_target_feature)), + ("power8-altivec", Some(sym::powerpc_target_feature)), +@@ -225,6 +230,7 @@ pub fn all_known_features() -> impl Iterator &'static [(&'static str, Opt + "riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES, + "wasm32" | "wasm64" => WASM_ALLOWED_FEATURES, + "bpf" => BPF_ALLOWED_FEATURES, ++ "loongarch64" => LOONGARCH64_ALLOWED_FEATURES, + _ => &[], + } + } +diff --git a/compiler/rustc_feature/src/active.rs b/compiler/rustc_feature/src/active.rs +index 0ba764021..61e09607f 100644 +--- a/compiler/rustc_feature/src/active.rs ++++ b/compiler/rustc_feature/src/active.rs +@@ -271,6 +271,7 @@ declare_features! ( + (active, riscv_target_feature, "1.45.0", Some(44839), None), + (active, ermsb_target_feature, "1.49.0", Some(44839), None), + (active, bpf_target_feature, "1.54.0", Some(44839), None), ++ //(active, loongarch64_target_feature, "1.57.0", Some(44839), None), + + // ------------------------------------------------------------------------- + // feature-group-end: actual feature gates (target features) +diff --git a/compiler/rustc_llvm/build.rs b/compiler/rustc_llvm/build.rs +index 36a6d2cc3..052da337d 100644 +--- a/compiler/rustc_llvm/build.rs ++++ b/compiler/rustc_llvm/build.rs +@@ -76,6 +76,7 @@ fn main() { + "aarch64", + "amdgpu", + "avr", ++ "loongarch", + "m68k", + "mips", + "powerpc", +diff --git a/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp b/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp +index 87f423fb2..39e946511 100644 +--- a/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp ++++ b/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp +@@ -251,6 +251,12 @@ void LLVMRustAddLastExtensionPasses( + #define SUBTARGET_HEXAGON + #endif + ++#ifdef LLVM_COMPONENT_LOONGARCH ++#define SUBTARGET_LOONGARCH SUBTARGET(LoongArch) ++#else ++#define SUBTARGET_LOONGARCH ++#endif ++ + #define GEN_SUBTARGETS \ + SUBTARGET_X86 \ + SUBTARGET_ARM \ +@@ -264,6 +270,7 @@ void LLVMRustAddLastExtensionPasses( + SUBTARGET_SPARC \ + SUBTARGET_HEXAGON \ + SUBTARGET_RISCV \ ++ SUBTARGET_LOONGARCH \ + + #define SUBTARGET(x) \ + namespace llvm { \ +diff --git a/compiler/rustc_llvm/src/lib.rs b/compiler/rustc_llvm/src/lib.rs +index 6493bd91c..7fff370c7 100644 +--- a/compiler/rustc_llvm/src/lib.rs ++++ b/compiler/rustc_llvm/src/lib.rs +@@ -102,6 +102,14 @@ pub fn initialize_available_targets() { + LLVMInitializeM68kAsmPrinter, + LLVMInitializeM68kAsmParser + ); ++ init_target!( ++ llvm_component = "loongarch", ++ LLVMInitializeLoongArchTargetInfo, ++ LLVMInitializeLoongArchTarget, ++ LLVMInitializeLoongArchTargetMC, ++ LLVMInitializeLoongArchAsmPrinter, ++ LLVMInitializeLoongArchAsmParser ++ ); + init_target!( + llvm_component = "mips", + LLVMInitializeMipsTargetInfo, +diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs +index 16205ad1c..389cf6b28 100644 +--- a/compiler/rustc_span/src/symbol.rs ++++ b/compiler/rustc_span/src/symbol.rs +@@ -785,6 +785,7 @@ symbols! { + log_syntax, + logf32, + logf64, ++ loongarch64_target_feature, + loop_break_value, + lt, + macro_at_most_once_rep, +diff --git a/compiler/rustc_target/src/abi/call/loongarch.rs b/compiler/rustc_target/src/abi/call/loongarch.rs +new file mode 100644 +index 000000000..2823fbf8a +--- /dev/null ++++ b/compiler/rustc_target/src/abi/call/loongarch.rs +@@ -0,0 +1,343 @@ ++use crate::abi::call::{ArgAbi, ArgExtension, CastTarget, FnAbi, PassMode, Reg, RegKind, Uniform}; ++use crate::abi::{self, Abi, FieldsShape, HasDataLayout, Size, TyAbiInterface, TyAndLayout}; ++use crate::spec::HasTargetSpec; ++ ++#[derive(Copy, Clone)] ++enum RegPassKind { ++ Float(Reg), ++ Integer(Reg), ++ Unknown, ++} ++ ++#[derive(Copy, Clone)] ++enum FloatConv { ++ FloatPair(Reg, Reg), ++ Float(Reg), ++ MixedPair(Reg, Reg), ++} ++ ++#[derive(Copy, Clone)] ++struct CannotUseFpConv; ++ ++fn is_loongarch_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool { ++ match arg.layout.abi { ++ Abi::Vector { .. } => true, ++ _ => arg.layout.is_aggregate(), ++ } ++} ++ ++fn should_use_fp_conv_helper<'a, Ty, C>( ++ cx: &C, ++ arg_layout: &TyAndLayout<'a, Ty>, ++ xlen: u64, ++ flen: u64, ++ field1_kind: &mut RegPassKind, ++ field2_kind: &mut RegPassKind, ++) -> Result<(), CannotUseFpConv> ++where ++ Ty: TyAbiInterface<'a, C> + Copy, ++{ ++ match arg_layout.abi { ++ Abi::Scalar(scalar) => match scalar.value { ++ abi::Int(..) | abi::Pointer => { ++ if arg_layout.size.bits() > xlen { ++ return Err(CannotUseFpConv); ++ } ++ match (*field1_kind, *field2_kind) { ++ (RegPassKind::Unknown, _) => { ++ *field1_kind = RegPassKind::Integer(Reg { ++ kind: RegKind::Integer, ++ size: arg_layout.size, ++ }); ++ } ++ (RegPassKind::Float(_), RegPassKind::Unknown) => { ++ *field2_kind = RegPassKind::Integer(Reg { ++ kind: RegKind::Integer, ++ size: arg_layout.size, ++ }); ++ } ++ _ => return Err(CannotUseFpConv), ++ } ++ } ++ abi::F32 | abi::F64 => { ++ if arg_layout.size.bits() > flen { ++ return Err(CannotUseFpConv); ++ } ++ match (*field1_kind, *field2_kind) { ++ (RegPassKind::Unknown, _) => { ++ *field1_kind = ++ RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size }); ++ } ++ (_, RegPassKind::Unknown) => { ++ *field2_kind = ++ RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size }); ++ } ++ _ => return Err(CannotUseFpConv), ++ } ++ } ++ }, ++ Abi::Vector { .. } | Abi::Uninhabited => return Err(CannotUseFpConv), ++ Abi::ScalarPair(..) | Abi::Aggregate { .. } => match arg_layout.fields { ++ FieldsShape::Primitive => { ++ unreachable!("aggregates can't have `FieldsShape::Primitive`") ++ } ++ FieldsShape::Union(_) => { ++ if !arg_layout.is_zst() { ++ return Err(CannotUseFpConv); ++ } ++ } ++ FieldsShape::Array { count, .. } => { ++ for _ in 0..count { ++ let elem_layout = arg_layout.field(cx, 0); ++ should_use_fp_conv_helper( ++ cx, ++ &elem_layout, ++ xlen, ++ flen, ++ field1_kind, ++ field2_kind, ++ )?; ++ } ++ } ++ FieldsShape::Arbitrary { .. } => { ++ match arg_layout.variants { ++ abi::Variants::Multiple { .. } => return Err(CannotUseFpConv), ++ abi::Variants::Single { .. } => (), ++ } ++ for i in arg_layout.fields.index_by_increasing_offset() { ++ let field = arg_layout.field(cx, i); ++ should_use_fp_conv_helper(cx, &field, xlen, flen, field1_kind, field2_kind)?; ++ } ++ } ++ }, ++ } ++ Ok(()) ++} ++ ++fn should_use_fp_conv<'a, Ty, C>( ++ cx: &C, ++ arg: &TyAndLayout<'a, Ty>, ++ xlen: u64, ++ flen: u64, ++) -> Option ++where ++ Ty: TyAbiInterface<'a, C> + Copy, ++{ ++ let mut field1_kind = RegPassKind::Unknown; ++ let mut field2_kind = RegPassKind::Unknown; ++ if should_use_fp_conv_helper(cx, arg, xlen, flen, &mut field1_kind, &mut field2_kind).is_err() { ++ return None; ++ } ++ match (field1_kind, field2_kind) { ++ (RegPassKind::Integer(l), RegPassKind::Float(r)) => Some(FloatConv::MixedPair(l, r)), ++ (RegPassKind::Float(l), RegPassKind::Integer(r)) => Some(FloatConv::MixedPair(l, r)), ++ (RegPassKind::Float(l), RegPassKind::Float(r)) => Some(FloatConv::FloatPair(l, r)), ++ (RegPassKind::Float(f), RegPassKind::Unknown) => Some(FloatConv::Float(f)), ++ _ => None, ++ } ++} ++ ++fn classify_ret<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, xlen: u64, flen: u64) -> bool ++where ++ Ty: TyAbiInterface<'a, C> + Copy, ++{ ++ if let Some(conv) = should_use_fp_conv(cx, &arg.layout, xlen, flen) { ++ match conv { ++ FloatConv::Float(f) => { ++ arg.cast_to(f); ++ } ++ FloatConv::FloatPair(l, r) => { ++ arg.cast_to(CastTarget::pair(l, r)); ++ } ++ FloatConv::MixedPair(l, r) => { ++ arg.cast_to(CastTarget::pair(l, r)); ++ } ++ } ++ return false; ++ } ++ ++ let total = arg.layout.size; ++ ++ // "Scalars wider than 2✕XLEN are passed by reference and are replaced in ++ // the argument list with the address." ++ // "Aggregates larger than 2✕XLEN bits are passed by reference and are ++ // replaced in the argument list with the address, as are C++ aggregates ++ // with nontrivial copy constructors, destructors, or vtables." ++ if total.bits() > 2 * xlen { ++ // We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN. ++ if is_loongarch_aggregate(arg) { ++ arg.make_indirect(); ++ } ++ return true; ++ } ++ ++ let xlen_reg = match xlen { ++ 32 => Reg::i32(), ++ 64 => Reg::i64(), ++ _ => unreachable!("Unsupported XLEN: {}", xlen), ++ }; ++ if is_loongarch_aggregate(arg) { ++ if total.bits() <= xlen { ++ arg.cast_to(xlen_reg); ++ } else { ++ arg.cast_to(Uniform { unit: xlen_reg, total: Size::from_bits(xlen * 2) }); ++ } ++ return false; ++ } ++ ++ // "When passed in registers, scalars narrower than XLEN bits are widened ++ // according to the sign of their type up to 32 bits, then sign-extended to ++ // XLEN bits." ++ extend_integer_width(arg, xlen); ++ false ++} ++ ++fn classify_arg<'a, Ty, C>( ++ cx: &C, ++ arg: &mut ArgAbi<'a, Ty>, ++ xlen: u64, ++ flen: u64, ++ is_vararg: bool, ++ avail_gprs: &mut u64, ++ avail_fprs: &mut u64, ++) where ++ Ty: TyAbiInterface<'a, C> + Copy, ++{ ++ if !is_vararg { ++ match should_use_fp_conv(cx, &arg.layout, xlen, flen) { ++ Some(FloatConv::Float(f)) if *avail_fprs >= 1 => { ++ *avail_fprs -= 1; ++ arg.cast_to(f); ++ return; ++ } ++ Some(FloatConv::FloatPair(l, r)) if *avail_fprs >= 2 => { ++ *avail_fprs -= 2; ++ arg.cast_to(CastTarget::pair(l, r)); ++ return; ++ } ++ Some(FloatConv::MixedPair(l, r)) if *avail_fprs >= 1 && *avail_gprs >= 1 => { ++ *avail_gprs -= 1; ++ *avail_fprs -= 1; ++ arg.cast_to(CastTarget::pair(l, r)); ++ return; ++ } ++ _ => (), ++ } ++ } ++ ++ let total = arg.layout.size; ++ let align = arg.layout.align.abi.bits(); ++ ++ // "Scalars wider than 2✕XLEN are passed by reference and are replaced in ++ // the argument list with the address." ++ // "Aggregates larger than 2✕XLEN bits are passed by reference and are ++ // replaced in the argument list with the address, as are C++ aggregates ++ // with nontrivial copy constructors, destructors, or vtables." ++ if total.bits() > 2 * xlen { ++ // We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN. ++ if is_loongarch_aggregate(arg) { ++ arg.make_indirect(); ++ } ++ if *avail_gprs >= 1 { ++ *avail_gprs -= 1; ++ } ++ return; ++ } ++ ++ let double_xlen_reg = match xlen { ++ 32 => Reg::i64(), ++ 64 => Reg::i128(), ++ _ => unreachable!("Unsupported XLEN: {}", xlen), ++ }; ++ ++ let xlen_reg = match xlen { ++ 32 => Reg::i32(), ++ 64 => Reg::i64(), ++ _ => unreachable!("Unsupported XLEN: {}", xlen), ++ }; ++ ++ if total.bits() > xlen { ++ let align_regs = align > xlen; ++ if is_loongarch_aggregate(arg) { ++ arg.cast_to(Uniform { ++ unit: if align_regs { double_xlen_reg } else { xlen_reg }, ++ total: Size::from_bits(xlen * 2), ++ }); ++ } ++ if align_regs && is_vararg { ++ *avail_gprs -= *avail_gprs % 2; ++ } ++ if *avail_gprs >= 2 { ++ *avail_gprs -= 2; ++ } else { ++ *avail_gprs = 0; ++ } ++ return; ++ } else if is_loongarch_aggregate(arg) { ++ arg.cast_to(xlen_reg); ++ if *avail_gprs >= 1 { ++ *avail_gprs -= 1; ++ } ++ return; ++ } ++ ++ // "When passed in registers, scalars narrower than XLEN bits are widened ++ // according to the sign of their type up to 32 bits, then sign-extended to ++ // XLEN bits." ++ if *avail_gprs >= 1 { ++ extend_integer_width(arg, xlen); ++ *avail_gprs -= 1; ++ } ++} ++ ++fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) { ++ if let Abi::Scalar(scalar) = arg.layout.abi { ++ if let abi::Int(i, _) = scalar.value { ++ // 32-bit integers are always sign-extended ++ if i.size().bits() == 32 && xlen > 32 { ++ if let PassMode::Direct(ref mut attrs) = arg.mode { ++ attrs.ext(ArgExtension::Sext); ++ return; ++ } ++ } ++ } ++ } ++ ++ arg.extend_integer_width_to(xlen); ++} ++ ++pub fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>) ++where ++ Ty: TyAbiInterface<'a, C> + Copy, ++ C: HasDataLayout + HasTargetSpec, ++{ ++ let xlen = cx.data_layout().pointer_size.bits(); ++ let flen = match &cx.target_spec().llvm_abiname[..] { ++ "ilp32d" | "lp64f" => 64, ++ "ilp32f" | "lp64d" => 32, ++ _ => 0, ++ }; ++ ++ let mut avail_gprs = 8; ++ let mut avail_fprs = 8; ++ ++ if !fn_abi.ret.is_ignore() && classify_ret(cx, &mut fn_abi.ret, xlen, flen) { ++ avail_gprs -= 1; ++ } ++ ++ for (i, arg) in fn_abi.args.iter_mut().enumerate() { ++ if arg.is_ignore() { ++ continue; ++ } ++ classify_arg( ++ cx, ++ arg, ++ xlen, ++ flen, ++ i >= fn_abi.fixed_count, ++ &mut avail_gprs, ++ &mut avail_fprs, ++ ); ++ } ++} ++ +diff --git a/compiler/rustc_target/src/abi/call/mod.rs b/compiler/rustc_target/src/abi/call/mod.rs +index d9eb299e2..362d0e6fe 100644 +--- a/compiler/rustc_target/src/abi/call/mod.rs ++++ b/compiler/rustc_target/src/abi/call/mod.rs +@@ -9,6 +9,7 @@ mod arm; + mod avr; + mod bpf; + mod hexagon; ++mod loongarch; + mod m68k; + mod mips; + mod mips64; +@@ -657,6 +658,7 @@ impl<'a, Ty> FnAbi<'a, Ty> { + "amdgpu" => amdgpu::compute_abi_info(cx, self), + "arm" => arm::compute_abi_info(cx, self), + "avr" => avr::compute_abi_info(self), ++ "loongarch64" => loongarch::compute_abi_info(cx, self), + "m68k" => m68k::compute_abi_info(self), + "mips" => mips::compute_abi_info(cx, self), + "mips64" => mips64::compute_abi_info(cx, self), +diff --git a/compiler/rustc_target/src/asm/loongarch.rs b/compiler/rustc_target/src/asm/loongarch.rs +new file mode 100644 +index 000000000..262d80eab +--- /dev/null ++++ b/compiler/rustc_target/src/asm/loongarch.rs +@@ -0,0 +1,130 @@ ++use super::{InlineAsmArch, InlineAsmType}; ++use rustc_macros::HashStable_Generic; ++use std::fmt; ++ ++def_reg_class! { ++ LoongArch LoongArchInlineAsmRegClass { ++ reg, ++ freg, ++ } ++} ++ ++impl LoongArchInlineAsmRegClass { ++ pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] { ++ &[] ++ } ++ ++ pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option { ++ None ++ } ++ ++ pub fn suggest_modifier( ++ self, ++ _arch: InlineAsmArch, ++ _ty: InlineAsmType, ++ ) -> Option<(char, &'static str)> { ++ None ++ } ++ ++ pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> { ++ None ++ } ++ ++ pub fn supported_types( ++ self, ++ arch: InlineAsmArch, ++ ) -> &'static [(InlineAsmType, Option<&'static str>)] { ++ match (self, arch) { ++ (Self::reg, InlineAsmArch::LoongArch64) => types! { _: I8, I16, I32, I64, F32, F64; }, ++ (Self::reg, _) => types! { _: I8, I16, I32, F32; }, ++ (Self::freg, _) => types! { _: F32, F64; }, ++ } ++ } ++} ++ ++// The reserved registers are taken from ++def_regs! { ++ LoongArch LoongArchInlineAsmReg LoongArchInlineAsmRegClass { ++ r1: reg = ["$r1","$ra"], ++ r4: reg = ["$r4","$a0"], ++ r5: reg = ["$r5","$a1"], ++ r6: reg = ["$r6","$a2"], ++ r7: reg = ["$r7","$a3"], ++ r8: reg = ["$r8","$a4"], ++ r9: reg = ["$r9","$a5"], ++ r10: reg = ["$r10","$a6"], ++ r11: reg = ["$r11","$a7"], ++ r12: reg = ["$r12","$t0"], ++ r13: reg = ["$r13","$t1"], ++ r14: reg = ["$r14","$t2"], ++ r15: reg = ["$r15","$t3"], ++ r16: reg = ["$r16","$t4"], ++ r17: reg = ["$r17","$t5"], ++ r18: reg = ["$r18","$t6"], ++ r19: reg = ["$r19","$t7"], ++ r20: reg = ["$r20","$t8"], ++ r23: reg = ["$r23","$s0"], ++ r24: reg = ["$r24","$s1"], ++ r25: reg = ["$r25","$s2"], ++ r26: reg = ["$r26","$s3"], ++ r27: reg = ["$r27","$s4"], ++ r28: reg = ["$r28","$s5"], ++ r29: reg = ["$r29","$s6"], ++ r30: reg = ["$r30","$s7"], ++ f0: freg = ["$f0","$fa0"], ++ f1: freg = ["$f1","$fa1"], ++ f2: freg = ["$f2","$fa2"], ++ f3: freg = ["$f3","$fa3"], ++ f4: freg = ["$f4","$fa4"], ++ f5: freg = ["$f5","$fa5"], ++ f6: freg = ["$f6","$fa6"], ++ f7: freg = ["$f7","$fa7"], ++ f8: freg = ["$f8","$ft0"], ++ f9: freg = ["$f9","$ft1"], ++ f10: freg = ["$f10","$ft2"], ++ f11: freg = ["$f11","$ft3"], ++ f12: freg = ["$f12","$ft4"], ++ f13: freg = ["$f13","$ft5"], ++ f14: freg = ["$f14","$ft6"], ++ f15: freg = ["$f15","$ft7"], ++ f16: freg = ["$f16","$ft8"], ++ f17: freg = ["$f17","$ft9"], ++ f18: freg = ["$f18","$ft10"], ++ f19: freg = ["$f19","$ft11"], ++ f20: freg = ["$f20","$ft12"], ++ f21: freg = ["$f21","$ft13"], ++ f22: freg = ["$f22","$ft14"], ++ f23: freg = ["$f23","$ft15"], ++ f24: freg = ["$f24","$fs0"], ++ f25: freg = ["$f25","$fs1"], ++ f26: freg = ["$f26","$fs2"], ++ f27: freg = ["$f27","$fs3"], ++ f28: freg = ["$f28","$fs4"], ++ f29: freg = ["$f29","$fs5"], ++ f30: freg = ["$f30","$fs6"], ++ f31: freg = ["$f31","$fs7"], ++ #error = ["$r0", "$zero"] => ++ "constant zero cannot be used as an operand for inline asm", ++ #error = ["$r2", "$tp"] => ++ "reserved for TLS", ++ #error = ["$r3", "$sp"] => ++ "the stack pointer cannot be used as an operand for inline asm", ++ #error = ["$r21", "$x"] => ++ "reserved for ABI extension", ++ #error = ["$r22", "$fp"] => ++ "the frame pointer cannot be used as an operand for inline asm", ++ #error = ["$r31", "$s8"] => ++ "r31 is used internally by LLVM and cannot be used as an operand for inline asm", ++ } ++} ++ ++impl LoongArchInlineAsmReg { ++ pub fn emit( ++ self, ++ out: &mut dyn fmt::Write, ++ _arch: InlineAsmArch, ++ _modifier: Option, ++ ) -> fmt::Result { ++ out.write_str(self.name()) ++ } ++} +diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs +index 99699c50d..e23d23b77 100644 +--- a/compiler/rustc_target/src/asm/mod.rs ++++ b/compiler/rustc_target/src/asm/mod.rs +@@ -150,6 +150,7 @@ mod aarch64; + mod arm; + mod bpf; + mod hexagon; ++mod loongarch; + mod mips; + mod nvptx; + mod powerpc; +@@ -163,6 +164,7 @@ pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass}; + pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass}; + pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass}; + pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass}; ++pub use loongarch::{LoongArchInlineAsmReg, LoongArchInlineAsmRegClass}; + pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass}; + pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass}; + pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass}; +@@ -190,6 +192,7 @@ pub enum InlineAsmArch { + SpirV, + Wasm32, + Bpf, ++ LoongArch64, + } + + impl FromStr for InlineAsmArch { +@@ -207,6 +210,7 @@ impl FromStr for InlineAsmArch { + "powerpc" => Ok(Self::PowerPC), + "powerpc64" => Ok(Self::PowerPC64), + "hexagon" => Ok(Self::Hexagon), ++ "loongarch64" => Ok(Self::LoongArch64), + "mips" => Ok(Self::Mips), + "mips64" => Ok(Self::Mips64), + "s390x" => Ok(Self::S390x), +@@ -238,6 +242,7 @@ pub enum InlineAsmReg { + Nvptx(NvptxInlineAsmReg), + PowerPC(PowerPCInlineAsmReg), + Hexagon(HexagonInlineAsmReg), ++ LoongArch(LoongArchInlineAsmReg), + Mips(MipsInlineAsmReg), + S390x(S390xInlineAsmReg), + SpirV(SpirVInlineAsmReg), +@@ -256,6 +261,7 @@ impl InlineAsmReg { + Self::RiscV(r) => r.name(), + Self::PowerPC(r) => r.name(), + Self::Hexagon(r) => r.name(), ++ Self::LoongArch(r) => r.name(), + Self::Mips(r) => r.name(), + Self::S390x(r) => r.name(), + Self::Bpf(r) => r.name(), +@@ -271,6 +277,7 @@ impl InlineAsmReg { + Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()), + Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()), + Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()), ++ Self::LoongArch(r) => InlineAsmRegClass::LoongArch(r.reg_class()), + Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()), + Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()), + Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()), +@@ -309,6 +316,9 @@ impl InlineAsmReg { + InlineAsmArch::Hexagon => { + Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?) + } ++ InlineAsmArch::LoongArch64 => { ++ Self::LoongArch(LoongArchInlineAsmReg::parse(arch, has_feature, target, &name)?) ++ } + InlineAsmArch::Mips | InlineAsmArch::Mips64 => { + Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?) + } +@@ -342,6 +352,7 @@ impl InlineAsmReg { + Self::RiscV(r) => r.emit(out, arch, modifier), + Self::PowerPC(r) => r.emit(out, arch, modifier), + Self::Hexagon(r) => r.emit(out, arch, modifier), ++ Self::LoongArch(r) => r.emit(out, arch, modifier), + Self::Mips(r) => r.emit(out, arch, modifier), + Self::S390x(r) => r.emit(out, arch, modifier), + Self::Bpf(r) => r.emit(out, arch, modifier), +@@ -357,6 +368,7 @@ impl InlineAsmReg { + Self::RiscV(_) => cb(self), + Self::PowerPC(r) => r.overlapping_regs(|r| cb(Self::PowerPC(r))), + Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))), ++ Self::LoongArch(_) => cb(self), + Self::Mips(_) => cb(self), + Self::S390x(_) => cb(self), + Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))), +@@ -385,6 +397,7 @@ pub enum InlineAsmRegClass { + Nvptx(NvptxInlineAsmRegClass), + PowerPC(PowerPCInlineAsmRegClass), + Hexagon(HexagonInlineAsmRegClass), ++ LoongArch(LoongArchInlineAsmRegClass), + Mips(MipsInlineAsmRegClass), + S390x(S390xInlineAsmRegClass), + SpirV(SpirVInlineAsmRegClass), +@@ -404,6 +417,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.name(), + Self::PowerPC(r) => r.name(), + Self::Hexagon(r) => r.name(), ++ Self::LoongArch(r) => r.name(), + Self::Mips(r) => r.name(), + Self::S390x(r) => r.name(), + Self::SpirV(r) => r.name(), +@@ -425,6 +439,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx), + Self::PowerPC(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::PowerPC), + Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon), ++ Self::LoongArch(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::LoongArch), + Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips), + Self::S390x(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::S390x), + Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV), +@@ -453,6 +468,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.suggest_modifier(arch, ty), + Self::PowerPC(r) => r.suggest_modifier(arch, ty), + Self::Hexagon(r) => r.suggest_modifier(arch, ty), ++ Self::LoongArch(r) => r.suggest_modifier(arch, ty), + Self::Mips(r) => r.suggest_modifier(arch, ty), + Self::S390x(r) => r.suggest_modifier(arch, ty), + Self::SpirV(r) => r.suggest_modifier(arch, ty), +@@ -477,6 +493,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.default_modifier(arch), + Self::PowerPC(r) => r.default_modifier(arch), + Self::Hexagon(r) => r.default_modifier(arch), ++ Self::LoongArch(r) => r.default_modifier(arch), + Self::Mips(r) => r.default_modifier(arch), + Self::S390x(r) => r.default_modifier(arch), + Self::SpirV(r) => r.default_modifier(arch), +@@ -500,6 +517,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.supported_types(arch), + Self::PowerPC(r) => r.supported_types(arch), + Self::Hexagon(r) => r.supported_types(arch), ++ Self::LoongArch(r) => r.supported_types(arch), + Self::Mips(r) => r.supported_types(arch), + Self::S390x(r) => r.supported_types(arch), + Self::SpirV(r) => r.supported_types(arch), +@@ -524,6 +542,7 @@ impl InlineAsmRegClass { + Self::PowerPC(PowerPCInlineAsmRegClass::parse(arch, name)?) + } + InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?), ++ InlineAsmArch::LoongArch64 => Self::LoongArch(LoongArchInlineAsmRegClass::parse(arch, name)?), + InlineAsmArch::Mips | InlineAsmArch::Mips64 => { + Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?) + } +@@ -545,6 +564,7 @@ impl InlineAsmRegClass { + Self::Nvptx(r) => r.valid_modifiers(arch), + Self::PowerPC(r) => r.valid_modifiers(arch), + Self::Hexagon(r) => r.valid_modifiers(arch), ++ Self::LoongArch(r) => r.valid_modifiers(arch), + Self::Mips(r) => r.valid_modifiers(arch), + Self::S390x(r) => r.valid_modifiers(arch), + Self::SpirV(r) => r.valid_modifiers(arch), +@@ -710,6 +730,11 @@ pub fn allocatable_registers( + hexagon::fill_reg_map(arch, has_feature, target, &mut map); + map + } ++ InlineAsmArch::LoongArch64 => { ++ let mut map = loongarch::regclass_map(); ++ loongarch::fill_reg_map(arch, has_feature, target, &mut map); ++ map ++ } + InlineAsmArch::Mips | InlineAsmArch::Mips64 => { + let mut map = mips::regclass_map(); + mips::fill_reg_map(arch, has_feature, target, &mut map); +diff --git a/compiler/rustc_target/src/spec/loongarch64_unknown_linux_gnuf64.rs b/compiler/rustc_target/src/spec/loongarch64_unknown_linux_gnuf64.rs +new file mode 100644 +index 000000000..7c6ac9e15 +--- /dev/null ++++ b/compiler/rustc_target/src/spec/loongarch64_unknown_linux_gnuf64.rs +@@ -0,0 +1,19 @@ ++use crate::spec::{CodeModel, Target, TargetOptions}; ++ ++pub fn target() -> Target { ++ Target { ++ llvm_target: "loongarch64-unknown-linux-gnuf64".into(), ++ pointer_width: 64, ++ data_layout: "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128".into(), ++ arch: "loongarch64".into(), ++ options: TargetOptions { ++ code_model: Some(CodeModel::Medium), ++// cpu: "generic-la64".into(), ++ cpu: "la464".into(), ++ features: "+d".into(), ++ llvm_abiname: "lp64d".into(), ++ max_atomic_width: Some(64), ++ ..super::linux_gnu_base::opts() ++ }, ++ } ++} +\ No newline at end of file +diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs +index ff5dfa3f7..772cc4274 100644 +--- a/compiler/rustc_target/src/spec/mod.rs ++++ b/compiler/rustc_target/src/spec/mod.rs +@@ -790,6 +790,7 @@ supported_targets! { + ("mips64-unknown-linux-muslabi64", mips64_unknown_linux_muslabi64), + ("mips64el-unknown-linux-muslabi64", mips64el_unknown_linux_muslabi64), + ("hexagon-unknown-linux-musl", hexagon_unknown_linux_musl), ++ ("loongarch64-unknown-linux-gnuf64", loongarch64_unknown_linux_gnuf64), + + ("mips-unknown-linux-uclibc", mips_unknown_linux_uclibc), + ("mipsel-unknown-linux-uclibc", mipsel_unknown_linux_uclibc), +diff --git a/compiler/rustc_typeck/src/collect.rs b/compiler/rustc_typeck/src/collect.rs +index df7f2aea9..ee3835f68 100644 +--- a/compiler/rustc_typeck/src/collect.rs ++++ b/compiler/rustc_typeck/src/collect.rs +@@ -2602,6 +2602,7 @@ fn from_target_feature( + Some(sym::arm_target_feature) => rust_features.arm_target_feature, + Some(sym::aarch64_target_feature) => rust_features.aarch64_target_feature, + Some(sym::hexagon_target_feature) => rust_features.hexagon_target_feature, ++ //Some(sym::loongarch64_target_feature) => rust_features.loongarch64_target_feature, + Some(sym::powerpc_target_feature) => rust_features.powerpc_target_feature, + Some(sym::mips_target_feature) => rust_features.mips_target_feature, + Some(sym::riscv_target_feature) => rust_features.riscv_target_feature, +diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs +index 13b80c05d..4801f5043 100644 +--- a/library/core/src/lib.rs ++++ b/library/core/src/lib.rs +@@ -197,6 +197,7 @@ + #![feature(cmpxchg16b_target_feature)] + #![feature(f16c_target_feature)] + #![feature(hexagon_target_feature)] ++//#![feature(loongarch64_target_feature)] + #![feature(mips_target_feature)] + #![feature(powerpc_target_feature)] + #![feature(rtm_target_feature)] +diff --git a/library/panic_unwind/src/gcc.rs b/library/panic_unwind/src/gcc.rs +index 9d6ede73e..f7a2ce8cf 100644 +--- a/library/panic_unwind/src/gcc.rs ++++ b/library/panic_unwind/src/gcc.rs +@@ -123,6 +123,9 @@ const UNWIND_DATA_REG: (i32, i32) = (0, 1); // R0, R1 + #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))] + const UNWIND_DATA_REG: (i32, i32) = (10, 11); // x10, x11 + ++#[cfg(target_arch = "loongarch64")] ++const UNWIND_DATA_REG: (i32, i32) = (4, 5); // A0, A1 ++ + // The following code is based on GCC's C and C++ personality routines. For reference, see: + // https://github.com/gcc-mirror/gcc/blob/master/libstdc++-v3/libsupc++/eh_personality.cc + // https://github.com/gcc-mirror/gcc/blob/trunk/libgcc/unwind-c.c +diff --git a/library/std/src/env.rs b/library/std/src/env.rs +index 40b46878c..748874eea 100644 +--- a/library/std/src/env.rs ++++ b/library/std/src/env.rs +@@ -879,6 +879,7 @@ pub mod consts { + /// - x86_64 + /// - arm + /// - aarch64 ++ /// - loongarch64 + /// - m68k + /// - mips + /// - mips64 +diff --git a/library/std/src/os/linux/raw.rs b/library/std/src/os/linux/raw.rs +index cd92dcabd..1a38e97de 100644 +--- a/library/std/src/os/linux/raw.rs ++++ b/library/std/src/os/linux/raw.rs +@@ -232,6 +232,7 @@ mod arch { + } + + #[cfg(any( ++ target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "s390x", + target_arch = "sparc64", +diff --git a/library/std/src/sys/common/alloc.rs b/library/std/src/sys/common/alloc.rs +index 576667c01..5ace3e48a 100644 +--- a/library/std/src/sys/common/alloc.rs ++++ b/library/std/src/sys/common/alloc.rs +@@ -24,6 +24,7 @@ pub const MIN_ALIGN: usize = 8; + target_arch = "mips64", + target_arch = "s390x", + target_arch = "sparc64", ++ target_arch = "loongarch64", + target_arch = "riscv64" + )))] + pub const MIN_ALIGN: usize = 16; +diff --git a/library/unwind/src/libunwind.rs b/library/unwind/src/libunwind.rs +index 5e15fe75a..11f1c34c4 100644 +--- a/library/unwind/src/libunwind.rs ++++ b/library/unwind/src/libunwind.rs +@@ -66,6 +66,9 @@ pub const unwinder_private_data_size: usize = 20; + #[cfg(all(target_arch = "hexagon", target_os = "linux"))] + pub const unwinder_private_data_size: usize = 35; + ++#[cfg(target_arch = "loongarch64")] ++pub const unwinder_private_data_size: usize = 2; ++ + #[repr(C)] + pub struct _Unwind_Exception { + pub exception_class: _Unwind_Exception_Class, +diff --git a/src/bootstrap/bootstrap.py b/src/bootstrap/bootstrap.py +index 0170be967..952b77768 100644 +--- a/src/bootstrap/bootstrap.py ++++ b/src/bootstrap/bootstrap.py +@@ -277,6 +277,7 @@ def default_build_triple(verbose): + 'i486': 'i686', + 'i686': 'i686', + 'i786': 'i686', ++ 'loongarch64': 'loongarch64', + 'm68k': 'm68k', + 'powerpc': 'powerpc', + 'powerpc64': 'powerpc64', +diff --git a/src/bootstrap/native.rs b/src/bootstrap/native.rs +index 27c9bb250..4bfb4e45b 100644 +--- a/src/bootstrap/native.rs ++++ b/src/bootstrap/native.rs +@@ -158,7 +158,7 @@ impl Step for Llvm { + let llvm_targets = match &builder.config.llvm_targets { + Some(s) => s, + None => { +- "AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\ ++ "AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;\ + Sparc;SystemZ;WebAssembly;X86" + } + }; +diff --git a/src/ci/github-actions/ci.yml b/src/ci/github-actions/ci.yml +index eb16cf3c7..775f9cbf0 100644 +--- a/src/ci/github-actions/ci.yml ++++ b/src/ci/github-actions/ci.yml +@@ -335,6 +335,9 @@ jobs: + - name: dist-i686-linux + <<: *job-linux-xl + ++ - name: dist-loongarch64-linux ++ <<: *job-linux-xl ++ + - name: dist-mips-linux + <<: *job-linux-xl + +diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md +index bbeab598f..3cb8ecaed 100644 +--- a/src/doc/rustc/src/platform-support.md ++++ b/src/doc/rustc/src/platform-support.md +@@ -83,6 +83,7 @@ target | notes + `arm-unknown-linux-gnueabi` | ARMv6 Linux (kernel 3.2, glibc 2.17) + `arm-unknown-linux-gnueabihf` | ARMv6 Linux, hardfloat (kernel 3.2, glibc 2.17) + `armv7-unknown-linux-gnueabihf` | ARMv7 Linux, hardfloat (kernel 3.2, glibc 2.17) ++`loongarch64-unknown-linux-gnuf64` | LOONGARCH64 Linux (kernel 4.19, glibc 2.28) + `mips-unknown-linux-gnu` | MIPS Linux (kernel 4.4, glibc 2.23) + `mips64-unknown-linux-gnuabi64` | MIPS64 Linux, n64 ABI (kernel 4.4, glibc 2.23) + `mips64el-unknown-linux-gnuabi64` | MIPS64 (LE) Linux, n64 ABI (kernel 4.4, glibc 2.23) +diff --git a/src/librustdoc/clean/cfg.rs b/src/librustdoc/clean/cfg.rs +index 9b5ca0684..55b856c6c 100644 +--- a/src/librustdoc/clean/cfg.rs ++++ b/src/librustdoc/clean/cfg.rs +@@ -491,6 +491,7 @@ impl<'a> fmt::Display for Display<'a> { + "aarch64" => "AArch64", + "arm" => "ARM", + "asmjs" => "JavaScript", ++ "loongarch64" => "LoongArch64", + "m68k" => "M68k", + "mips" => "MIPS", + "mips64" => "MIPS-64", +diff --git a/src/test/assembly/asm/loongarch-types.rs b/src/test/assembly/asm/loongarch-types.rs +new file mode 100644 +index 000000000..34973b942 +--- /dev/null ++++ b/src/test/assembly/asm/loongarch-types.rs +@@ -0,0 +1,194 @@ ++// min-llvm-version: 10.0.1 ++// assembly-output: emit-asm ++// compile-flags: --target loongarch64-unknown-linux-gnuf64 ++// needs-llvm-components: loongarch ++ ++#![feature(no_core, lang_items, rustc_attrs)] ++#![crate_type = "rlib"] ++#![no_core] ++#![allow(asm_sub_register)] ++ ++#[rustc_builtin_macro] ++macro_rules! asm { ++ () => {}; ++} ++#[rustc_builtin_macro] ++macro_rules! concat { ++ () => {}; ++} ++#[rustc_builtin_macro] ++macro_rules! stringify { ++ () => {}; ++} ++ ++#[lang = "sized"] ++trait Sized {} ++#[lang = "copy"] ++trait Copy {} ++ ++type ptr = *const i32; ++ ++impl Copy for i8 {} ++impl Copy for i16 {} ++impl Copy for i32 {} ++impl Copy for i64 {} ++impl Copy for f32 {} ++impl Copy for f64 {} ++impl Copy for ptr {} ++extern "C" { ++ fn extern_func(); ++ static extern_static: u8; ++} ++ ++// Hack to avoid function merging ++extern "Rust" { ++ fn dont_merge(s: &str); ++} ++ ++// CHECK-LABEL: sym_fn: ++// CHECK: #APP ++// CHECK: la.got $r12, extern_func ++// CHECK: #NO_APP ++#[no_mangle] ++pub unsafe fn sym_fn() { ++ asm!("la.got $r12, {}", sym extern_func); ++} ++ ++// CHECK-LABEL: sym_static: ++// CHECK: #APP ++// CHECK: la.got $r12, extern_static ++// CHECK: #NO_APP ++#[no_mangle] ++pub unsafe fn sym_static() { ++ asm!("la.got $r12, {}", sym extern_static); ++} ++ ++macro_rules! check { ($func:ident, $ty:ty, $class:ident, $mov:literal) => { ++ #[no_mangle] ++ pub unsafe fn $func(x: $ty) -> $ty { ++ dont_merge(stringify!($func)); ++ ++ let y; ++ asm!(concat!($mov," {}, {}"), out($class) y, in($class) x); ++ y ++ } ++};} ++ ++macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt, $mov:literal) => { ++ #[no_mangle] ++ pub unsafe fn $func(x: $ty) -> $ty { ++ dont_merge(stringify!($func)); ++ ++ let y; ++ asm!(concat!($mov, " ", $reg, ", ", $reg), lateout($reg) y, in($reg) x); ++ y ++ } ++};} ++ ++// CHECK-LABEL: reg_i8: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_i8, i8, reg, "move"); ++ ++// CHECK-LABEL: reg_i16: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_i16, i16, reg, "move"); ++ ++// CHECK-LABEL: reg_i32: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_i32, i32, reg, "move"); ++ ++// CHECK-LABEL: reg_f32: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_f32, f32, reg, "move"); ++ ++// CHECK-LABEL: reg_i64: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_i64, i64, reg, "move"); ++ ++// CHECK-LABEL: reg_f64: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_f64, f64, reg, "move"); ++ ++// CHECK-LABEL: reg_ptr: ++// CHECK: #APP ++// CHECK: move $r{{[0-9]+}}, $r{{[0-9]+}} ++// CHECK: #NO_APP ++check!(reg_ptr, ptr, reg, "move"); ++ ++// CHECK-LABEL: freg_f32: ++// CHECK: #APP ++// CHECK: fmov.s $f{{[0-9]+}}, $f{{[0-9]+}} ++// CHECK: #NO_APP ++check!(freg_f32, f32, freg, "fmov.s"); ++ ++// CHECK-LABEL: freg_f64: ++// CHECK: #APP ++// CHECK: fmov.d $f{{[0-9]+}}, $f{{[0-9]+}} ++// CHECK: #NO_APP ++check!(freg_f64, f64, freg, "fmov.d"); ++ ++// CHECK-LABEL: r4_i8: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_i8, i8, "$r4", "move"); ++ ++// CHECK-LABEL: r4_i16: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_i16, i16, "$r4", "move"); ++ ++// CHECK-LABEL: r4_i32: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_i32, i32, "$r4", "move"); ++ ++// CHECK-LABEL: r4_f32: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_f32, f32, "$r4", "move"); ++ ++// CHECK-LABEL: r4_i64: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_i64, i64, "$r4", "move"); ++ ++// CHECK-LABEL: r4_f64: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_f64, f64, "$r4", "move"); ++ ++// CHECK-LABEL: r4_ptr: ++// CHECK: #APP ++// CHECK: move $r4, $r4 ++// CHECK: #NO_APP ++check_reg!(r4_ptr, ptr, "$r4", "move"); ++ ++// CHECK-LABEL: f0_f32: ++// CHECK: #APP ++// CHECK: fmov.s $f{{[0-9]+}}, $f{{[0-9]+}} ++// CHECK: #NO_APP ++check_reg!(f0_f32, f32, "$f0", "fmov.s"); ++ ++// CHECK-LABEL: f0_f64: ++// CHECK: #APP ++// CHECK: fmov.d $f{{[0-9]+}}, $f{{[0-9]+}} ++// CHECK: #NO_APP ++check_reg!(f0_f64, f64, "$f0", "fmov.d"); +diff --git a/src/test/codegen/abi-main-signature-16bit-c-int.rs b/src/test/codegen/abi-main-signature-16bit-c-int.rs +index 4ed491dfb..1b79aa221 100644 +--- a/src/test/codegen/abi-main-signature-16bit-c-int.rs ++++ b/src/test/codegen/abi-main-signature-16bit-c-int.rs +@@ -6,6 +6,7 @@ + // ignore-arm + // ignore-asmjs + // ignore-hexagon ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +diff --git a/src/test/codegen/call-llvm-intrinsics.rs b/src/test/codegen/call-llvm-intrinsics.rs +index 998099c23..77a11ad9f 100644 +--- a/src/test/codegen/call-llvm-intrinsics.rs ++++ b/src/test/codegen/call-llvm-intrinsics.rs +@@ -1,6 +1,7 @@ + // compile-flags: -C no-prepopulate-passes + + // ignore-riscv64 ++// ignore-loongarch64 + + #![feature(link_llvm_intrinsics)] + #![crate_type = "lib"] +diff --git a/src/test/codegen/fastcall-inreg.rs b/src/test/codegen/fastcall-inreg.rs +index adbeae454..deb353d0c 100644 +--- a/src/test/codegen/fastcall-inreg.rs ++++ b/src/test/codegen/fastcall-inreg.rs +@@ -10,6 +10,7 @@ + // ignore-bpfel + // ignore-bpfeb + // ignore-hexagon ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-msp430 +diff --git a/src/test/codegen/global_asm.rs b/src/test/codegen/global_asm.rs +index 57d8aeb16..ac235e02c 100644 +--- a/src/test/codegen/global_asm.rs ++++ b/src/test/codegen/global_asm.rs +@@ -6,6 +6,7 @@ + // ignore-bpfel + // ignore-bpfeb + // ignore-hexagon ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-msp430 +diff --git a/src/test/codegen/global_asm_include.rs b/src/test/codegen/global_asm_include.rs +index 44402619c..9a5daa3f3 100644 +--- a/src/test/codegen/global_asm_include.rs ++++ b/src/test/codegen/global_asm_include.rs +@@ -6,6 +6,7 @@ + // ignore-bpfel + // ignore-bpfeb + // ignore-hexagon ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-msp430 +diff --git a/src/test/codegen/global_asm_x2.rs b/src/test/codegen/global_asm_x2.rs +index d632d0dde..67f14e708 100644 +--- a/src/test/codegen/global_asm_x2.rs ++++ b/src/test/codegen/global_asm_x2.rs +@@ -6,6 +6,7 @@ + // ignore-bpfel + // ignore-bpfeb + // ignore-hexagon ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-msp430 +diff --git a/src/test/codegen/loongarch-abi/call-llvm-intrinsics.rs b/src/test/codegen/loongarch-abi/call-llvm-intrinsics.rs +new file mode 100644 +index 000000000..74aee760d +--- /dev/null ++++ b/src/test/codegen/loongarch-abi/call-llvm-intrinsics.rs +@@ -0,0 +1,30 @@ ++// compile-flags: -C no-prepopulate-passes ++ ++// only-loongarch64 ++ ++#![feature(link_llvm_intrinsics)] ++#![crate_type = "lib"] ++ ++struct A; ++ ++impl Drop for A { ++ fn drop(&mut self) { ++ println!("A"); ++ } ++} ++ ++extern "C" { ++ #[link_name = "llvm.sqrt.f32"] ++ fn sqrt(x: f32) -> f32; ++} ++ ++pub fn do_call() { ++ let _a = A; ++ ++ unsafe { ++ // Ensure that we `call` LLVM intrinsics instead of trying to `invoke` them ++ // CHECK: store float 4.000000e+00, float* %{{.}}, align 4 ++ // CHECK: call float @llvm.sqrt.f32(float %{{.}} ++ sqrt(4.0); ++ } ++} +diff --git a/src/test/codegen/repr-transparent-aggregates-1.rs b/src/test/codegen/repr-transparent-aggregates-1.rs +index 3017adb44..913ca18db 100644 +--- a/src/test/codegen/repr-transparent-aggregates-1.rs ++++ b/src/test/codegen/repr-transparent-aggregates-1.rs +@@ -4,6 +4,7 @@ + // min-system-llvm-version: 12.0 + // ignore-arm + // ignore-aarch64 ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +diff --git a/src/test/codegen/repr-transparent-aggregates-2.rs b/src/test/codegen/repr-transparent-aggregates-2.rs +index 429d760b4..901d3031f 100644 +--- a/src/test/codegen/repr-transparent-aggregates-2.rs ++++ b/src/test/codegen/repr-transparent-aggregates-2.rs +@@ -5,6 +5,7 @@ + // ignore-aarch64 + // ignore-emscripten + // ignore-mips64 ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/codegen/repr-transparent.rs b/src/test/codegen/repr-transparent.rs +index 7add522c1..2549bdc80 100644 +--- a/src/test/codegen/repr-transparent.rs ++++ b/src/test/codegen/repr-transparent.rs +@@ -2,6 +2,7 @@ + + // ignore-riscv64 riscv64 has an i128 type used with test_Vector + // see codegen/riscv-abi for riscv functiona call tests ++// ignore-loongarch64 + + #![crate_type="lib"] + #![feature(repr_simd, transparent_unions)] +diff --git a/src/test/codegen/stack-probes.rs b/src/test/codegen/stack-probes.rs +index 9bd351df3..d2bf8a1ba 100644 +--- a/src/test/codegen/stack-probes.rs ++++ b/src/test/codegen/stack-probes.rs +@@ -1,5 +1,6 @@ + // ignore-arm + // ignore-aarch64 ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +diff --git a/src/test/run-make-fulldeps/atomic-lock-free/Makefile b/src/test/run-make-fulldeps/atomic-lock-free/Makefile +index 9e8b4fabf..7091371c1 100644 +--- a/src/test/run-make-fulldeps/atomic-lock-free/Makefile ++++ b/src/test/run-make-fulldeps/atomic-lock-free/Makefile +@@ -25,6 +25,10 @@ ifeq ($(filter aarch64,$(LLVM_COMPONENTS)),aarch64) + $(RUSTC) --target=aarch64-unknown-linux-gnu atomic_lock_free.rs + nm "$(TMPDIR)/libatomic_lock_free.rlib" | $(CGREP) -v __atomic_fetch_add + endif ++ifeq ($(filter loongarch64,$(LLVM_COMPONENTS)),loongarch64) ++ $(RUSTC) --target=loongarch64-unknown-linux-gnuf64 atomic_lock_free.rs ++ nm "$(TMPDIR)/libatomic_lock_free.rlib" | $(CGREP) -v __atomic_fetch_add ++endif + ifeq ($(filter mips,$(LLVM_COMPONENTS)),mips) + $(RUSTC) --target=mips-unknown-linux-gnu atomic_lock_free.rs + nm "$(TMPDIR)/libatomic_lock_free.rlib" | $(CGREP) -v __atomic_fetch_add +diff --git a/src/test/ui/abi/stack-probes-lto.rs b/src/test/ui/abi/stack-probes-lto.rs +index 90df1f3f5..075a1a124 100644 +--- a/src/test/ui/abi/stack-probes-lto.rs ++++ b/src/test/ui/abi/stack-probes-lto.rs +@@ -1,6 +1,7 @@ + // run-pass + // ignore-arm + // ignore-aarch64 ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +diff --git a/src/test/ui/borrowck/borrowck-asm.rs b/src/test/ui/borrowck/borrowck-asm.rs +index 0d202c1b4..46a7c5f7b 100644 +--- a/src/test/ui/borrowck/borrowck-asm.rs ++++ b/src/test/ui/borrowck/borrowck-asm.rs +@@ -6,6 +6,7 @@ + // ignore-riscv64 + // ignore-sparc + // ignore-sparc64 ++// ignore-loongarch64 + + #![feature(llvm_asm)] + #![allow(deprecated)] // llvm_asm! +@@ -14,6 +15,7 @@ + target_arch = "x86_64", + target_arch = "arm", + target_arch = "aarch64", ++ target_arch = "loongarch64", + target_arch = "mips", + target_arch = "mips64"))] + mod test_cases { +diff --git a/src/test/ui/cfg/conditional-compile-arch.rs b/src/test/ui/cfg/conditional-compile-arch.rs +index 7de561df1..34172b8c9 100644 +--- a/src/test/ui/cfg/conditional-compile-arch.rs ++++ b/src/test/ui/cfg/conditional-compile-arch.rs +@@ -13,6 +13,9 @@ pub fn main() { } + #[cfg(target_arch = "aarch64")] + pub fn main() { } + ++#[cfg(target_arch = "loongarch64")] ++pub fn main() { } ++ + #[cfg(target_arch = "mips")] + pub fn main() { } + +diff --git a/src/test/ui/empty_global_asm.rs b/src/test/ui/empty_global_asm.rs +index efbe2b2eb..0675da123 100644 +--- a/src/test/ui/empty_global_asm.rs ++++ b/src/test/ui/empty_global_asm.rs +@@ -14,6 +14,9 @@ global_asm!(""); + #[cfg(target_arch = "aarch64")] + global_asm!(""); + ++#[cfg(target_arch = "loongarch64")] ++global_asm!(""); ++ + #[cfg(target_arch = "mips")] + global_asm!(""); + +diff --git a/src/test/ui/llvm-asm/llvm-asm-bad-clobber.rs b/src/test/ui/llvm-asm/llvm-asm-bad-clobber.rs +index c15009f15..a4e594b45 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-bad-clobber.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-bad-clobber.rs +@@ -3,6 +3,7 @@ + // ignore-aarch64 + // ignore-s390x + // ignore-emscripten ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/ui/llvm-asm/llvm-asm-in-bad-modifier.rs b/src/test/ui/llvm-asm/llvm-asm-in-bad-modifier.rs +index 1bccb0b73..9e57c1453 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-in-bad-modifier.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-in-bad-modifier.rs +@@ -1,5 +1,6 @@ + // ignore-s390x + // ignore-emscripten ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/ui/llvm-asm/llvm-asm-misplaced-option.rs b/src/test/ui/llvm-asm/llvm-asm-misplaced-option.rs +index 04f0972ed..a8d50f992 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-misplaced-option.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-misplaced-option.rs +@@ -2,6 +2,7 @@ + // ignore-android + // ignore-arm + // ignore-aarch64 ++// ignore-loongarch64 + // ignore-s390x + // ignore-emscripten + // ignore-powerpc +diff --git a/src/test/ui/llvm-asm/llvm-asm-out-assign-imm.rs b/src/test/ui/llvm-asm/llvm-asm-out-assign-imm.rs +index 7f51b50f2..da3838a0c 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-out-assign-imm.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-out-assign-imm.rs +@@ -1,5 +1,6 @@ + // ignore-s390x + // ignore-emscripten ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/ui/llvm-asm/llvm-asm-out-no-modifier.rs b/src/test/ui/llvm-asm/llvm-asm-out-no-modifier.rs +index c74d156cf..2f6a402b9 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-out-no-modifier.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-out-no-modifier.rs +@@ -1,5 +1,6 @@ + // ignore-s390x + // ignore-emscripten ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/ui/llvm-asm/llvm-asm-out-read-uninit.rs b/src/test/ui/llvm-asm/llvm-asm-out-read-uninit.rs +index 161add7e5..255187930 100644 +--- a/src/test/ui/llvm-asm/llvm-asm-out-read-uninit.rs ++++ b/src/test/ui/llvm-asm/llvm-asm-out-read-uninit.rs +@@ -1,5 +1,6 @@ + // ignore-s390x + // ignore-emscripten ++// ignore-loongarch64 + // ignore-powerpc + // ignore-powerpc64 + // ignore-powerpc64le +diff --git a/src/test/ui/target-feature/gate.rs b/src/test/ui/target-feature/gate.rs +index 7cdf40424..d959168c5 100644 +--- a/src/test/ui/target-feature/gate.rs ++++ b/src/test/ui/target-feature/gate.rs +@@ -2,6 +2,7 @@ + // ignore-aarch64 + // ignore-wasm + // ignore-emscripten ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +@@ -28,6 +29,7 @@ + // gate-test-riscv_target_feature + // gate-test-ermsb_target_feature + // gate-test-bpf_target_feature ++// gate-test-loongarch64_target_feature + + #[target_feature(enable = "avx512bw")] + //~^ ERROR: currently unstable +diff --git a/src/test/ui/target-feature/invalid-attribute.rs b/src/test/ui/target-feature/invalid-attribute.rs +index 5ea782155..a091ad8fe 100644 +--- a/src/test/ui/target-feature/invalid-attribute.rs ++++ b/src/test/ui/target-feature/invalid-attribute.rs +@@ -2,6 +2,7 @@ + // ignore-aarch64 + // ignore-wasm + // ignore-emscripten ++// ignore-loongarch64 + // ignore-mips + // ignore-mips64 + // ignore-powerpc +diff --git a/src/tools/build-manifest/src/main.rs b/src/tools/build-manifest/src/main.rs +index c1579ae9a..f90311c58 100644 +--- a/src/tools/build-manifest/src/main.rs ++++ b/src/tools/build-manifest/src/main.rs +@@ -28,6 +28,7 @@ static HOSTS: &[&str] = &[ + "i686-pc-windows-gnu", + "i686-pc-windows-msvc", + "i686-unknown-linux-gnu", ++ "loongarch64-unknown-linux-gnuf64", + "mips-unknown-linux-gnu", + "mips64-unknown-linux-gnuabi64", + "mips64el-unknown-linux-gnuabi64", +@@ -99,6 +100,7 @@ static TARGETS: &[&str] = &[ + "i686-unknown-freebsd", + "i686-unknown-linux-gnu", + "i686-unknown-linux-musl", ++ "loongarch64-unknown-linux-gnuf64", + "m68k-unknown-linux-gnu", + "mips-unknown-linux-gnu", + "mips-unknown-linux-musl", +diff --git a/src/tools/clippy/tests/ui/asm_syntax.rs b/src/tools/clippy/tests/ui/asm_syntax.rs +index 4a62f6f29..b76f18ddd 100644 +--- a/src/tools/clippy/tests/ui/asm_syntax.rs ++++ b/src/tools/clippy/tests/ui/asm_syntax.rs +@@ -1,5 +1,6 @@ + // only-x86_64 + // ignore-aarch64 ++// ignore-loongarch64 + + #![feature(asm)] + +diff --git a/src/tools/compiletest/src/json.rs b/src/tools/compiletest/src/json.rs +index dc6d67983..bc3fb38ca 100644 +--- a/src/tools/compiletest/src/json.rs ++++ b/src/tools/compiletest/src/json.rs +@@ -74,8 +74,8 @@ struct DiagnosticSpanMacroExpansion { + struct DiagnosticCode { + /// The code itself. + code: String, +- /// An explanation for the code. +- explanation: Option, ++// /// An explanation for the code. ++// explanation: Option, + } + + pub fn rustfix_diagnostics_only(output: &str) -> String { +diff --git a/src/tools/compiletest/src/util.rs b/src/tools/compiletest/src/util.rs +index d03c21dc5..46fcd5f28 100644 +--- a/src/tools/compiletest/src/util.rs ++++ b/src/tools/compiletest/src/util.rs +@@ -54,6 +54,7 @@ const ARCH_TABLE: &[(&str, &str)] = &[ + ("i386", "x86"), + ("i586", "x86"), + ("i686", "x86"), ++ ("loongarch64", "loongarch64"), + ("m68k", "m68k"), + ("mips", "mips"), + ("mips64", "mips64"), +@@ -133,7 +134,7 @@ const BIG_ENDIAN: &[&str] = &[ + ]; + + static ASM_SUPPORTED_ARCHS: &[&str] = &[ +- "x86", "x86_64", "arm", "aarch64", "riscv32", "riscv64", "nvptx64", "hexagon", "mips", ++ "x86", "x86_64", "arm", "aarch64", "riscv32", "riscv64", "nvptx64", "hexagon", "loongarch64", "mips", + "mips64", "spirv", "wasm32", + ]; + +diff --git a/src/tools/miri/src/shims/foreign_items.rs b/src/tools/miri/src/shims/foreign_items.rs +index 18f167323..25f02182f 100644 +--- a/src/tools/miri/src/shims/foreign_items.rs ++++ b/src/tools/miri/src/shims/foreign_items.rs +@@ -47,7 +47,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: crate::MiriEvalContextExt<'mir, 'tcx + // List taken from `libstd/sys_common/alloc.rs`. + let min_align = match this.tcx.sess.target.arch.as_str() { + "x86" | "arm" | "mips" | "powerpc" | "powerpc64" | "asmjs" | "wasm32" => 8, +- "x86_64" | "aarch64" | "mips64" | "s390x" | "sparc64" => 16, ++ "x86_64" | "aarch64" | "mips64" | "s390x" | "sparc64" | "loongarch64" => 16, + arch => bug!("Unsupported target architecture: {}", arch), + }; + // Windows always aligns, even small allocations. +-- +2.27.0 + diff --git a/0002-vendor-Add-loongarch64-support.patch b/0002-vendor-Add-loongarch64-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..0237b0ea933a5ec2db133156b1d077c3fc16d374 --- /dev/null +++ b/0002-vendor-Add-loongarch64-support.patch @@ -0,0 +1,1602 @@ +From f6f8760116f03c292b5f1feb1eddd1b2d824b0b8 Mon Sep 17 00:00:00 2001 +From: yangxiaojuan +Date: Thu, 22 Sep 2022 20:39:48 +0800 +Subject: [PATCH 2/2] vendor: Add loongarch64 support + +--- + vendor/cc-1.0.69/src/lib.rs | 1 + + vendor/compiletest_rs/src/util.rs | 1 + + vendor/gimli/src/arch.rs | 82 ++ + .../libc/src/unix/linux_like/linux/align.rs | 6 +- + .../linux/gnu/b64/loongarch64/align.rs | 7 + + .../linux/gnu/b64/loongarch64/mod.rs | 932 ++++++++++++++++++ + .../src/unix/linux_like/linux/gnu/b64/mod.rs | 5 + + .../libc/src/unix/linux_like/linux/gnu/mod.rs | 7 +- + .../src/unix/linux_like/linux/no_align.rs | 2 + + vendor/object/src/common.rs | 2 + + vendor/object/src/elf.rs | 197 ++++ + vendor/object/src/read/elf/file.rs | 1 + + vendor/object/src/read/elf/relocation.rs | 5 + + vendor/object/src/write/elf.rs | 10 + + vendor/object/tests/round_trip/mod.rs | 1 + + vendor/psm/build.rs | 1 + + vendor/psm/src/arch/loongarch64.s | 63 ++ + 17 files changed, 1320 insertions(+), 3 deletions(-) + create mode 100644 vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/align.rs + create mode 100644 vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/mod.rs + create mode 100644 vendor/psm/src/arch/loongarch64.s + +diff --git a/vendor/cc-1.0.69/src/lib.rs b/vendor/cc-1.0.69/src/lib.rs +index b62a1da04..aebf234cd 100644 +--- a/vendor/cc-1.0.69/src/lib.rs ++++ b/vendor/cc-1.0.69/src/lib.rs +@@ -2408,6 +2408,7 @@ impl Build { + "i686-uwp-windows-gnu" => Some("i686-w64-mingw32"), + "i686-unknown-linux-musl" => Some("musl"), + "i686-unknown-netbsd" => Some("i486--netbsdelf"), ++ "loongarch64-unknown-linux-gnuf64" => Some("loongarch64-linux-gnuf64"), + "mips-unknown-linux-gnu" => Some("mips-linux-gnu"), + "mips-unknown-linux-musl" => Some("mips-linux-musl"), + "mipsel-unknown-linux-gnu" => Some("mipsel-linux-gnu"), +diff --git a/vendor/compiletest_rs/src/util.rs b/vendor/compiletest_rs/src/util.rs +index fed8f7a52..387f81413 100644 +--- a/vendor/compiletest_rs/src/util.rs ++++ b/vendor/compiletest_rs/src/util.rs +@@ -41,6 +41,7 @@ const ARCH_TABLE: &'static [(&'static str, &'static str)] = &[ + ("i386", "x86"), + ("i586", "x86"), + ("i686", "x86"), ++ ("loongarch64", "loongarch64"), + ("mips", "mips"), + ("msp430", "msp430"), + ("nvptx64", "nvptx64"), +diff --git a/vendor/gimli/src/arch.rs b/vendor/gimli/src/arch.rs +index d30c3fc48..6e42dc566 100644 +--- a/vendor/gimli/src/arch.rs ++++ b/vendor/gimli/src/arch.rs +@@ -228,3 +228,85 @@ registers!(X86_64, { + K6 = (124, "k6"), + K7 = (125, "k7"), + }); ++ ++/// LoongArch architecture specific definitions. ++/// ++/// See [LoongArch ELF psABI specification](https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html). ++#[derive(Debug, Clone, Copy)] ++pub struct LoongArch; ++ ++registers!(LoongArch, { ++ R0 = (0, "$r0"), ++ R1 = (1, "$r1"), ++ R2 = (2, "$r2"), ++ R3 = (3, "$r3"), ++ R4 = (4, "$r4"), ++ R5 = (5, "$r5"), ++ R6 = (6, "$r6"), ++ R7 = (7, "$r7"), ++ R8 = (8, "$r8"), ++ R9 = (9, "$r9"), ++ R10 = (10, "$r10"), ++ R11 = (11, "$r11"), ++ R12 = (12, "$r12"), ++ R13 = (13, "$r13"), ++ R14 = (14, "$r14"), ++ R15 = (15, "$r15"), ++ R16 = (16, "$r16"), ++ R17 = (17, "$r17"), ++ R18 = (18, "$r18"), ++ R19 = (19, "$r19"), ++ R20 = (20, "$r20"), ++ R21 = (21, "$r21"), ++ R22 = (22, "$r22"), ++ R23 = (23, "$r23"), ++ R24 = (24, "$r24"), ++ R25 = (25, "$r25"), ++ R26 = (26, "$r26"), ++ R27 = (27, "$r27"), ++ R28 = (28, "$r28"), ++ R29 = (29, "$r29"), ++ R30 = (30, "$r30"), ++ R31 = (31, "$r31"), ++ ++ F0 = (32, "$f0"), ++ F1 = (33, "$f1"), ++ F2 = (34, "$f2"), ++ F3 = (35, "$f3"), ++ F4 = (36, "$f4"), ++ F5 = (37, "$f5"), ++ F6 = (38, "$f6"), ++ F7 = (39, "$f7"), ++ F8 = (40, "$f8"), ++ F9 = (41, "$f9"), ++ F10 = (42, "$f10"), ++ F11 = (43, "$f11"), ++ F12 = (44, "$f12"), ++ F13 = (45, "$f13"), ++ F14 = (46, "$f14"), ++ F15 = (47, "$f15"), ++ F16 = (48, "$f16"), ++ F17 = (49, "$f17"), ++ F18 = (50, "$f18"), ++ F19 = (51, "$f19"), ++ F20 = (52, "$f20"), ++ F21 = (53, "$f21"), ++ F22 = (54, "$f22"), ++ F23 = (55, "$f23"), ++ F24 = (56, "$f24"), ++ F25 = (57, "$f25"), ++ F26 = (58, "$f26"), ++ F27 = (59, "$f27"), ++ F28 = (60, "$f28"), ++ F29 = (61, "$f29"), ++ F30 = (62, "$f30"), ++ F31 = (63, "$f31"), ++ FCC0 = (64, "$fcc0"), ++ FCC1 = (65, "$fcc1"), ++ FCC2 = (66, "$fcc2"), ++ FCC3 = (67, "$fcc3"), ++ FCC4 = (68, "$fcc4"), ++ FCC5 = (69, "$fcc5"), ++ FCC6 = (70, "$fcc6"), ++ FCC7 = (71, "$fcc7"), ++}); +diff --git a/vendor/libc/src/unix/linux_like/linux/align.rs b/vendor/libc/src/unix/linux_like/linux/align.rs +index 11f5504a5..0b5638769 100644 +--- a/vendor/libc/src/unix/linux_like/linux/align.rs ++++ b/vendor/libc/src/unix/linux_like/linux/align.rs +@@ -9,7 +9,8 @@ macro_rules! expand_align { + target_arch = "sparc64", + target_arch = "aarch64", + target_arch = "riscv64", +- target_arch = "riscv32"), ++ target_arch = "riscv32", ++ target_arch = "loongarch64"), + repr(align(4)))] + #[cfg_attr(not(any(target_pointer_width = "32", + target_arch = "x86_64", +@@ -19,7 +20,8 @@ macro_rules! expand_align { + target_arch = "sparc64", + target_arch = "aarch64", + target_arch = "riscv64", +- target_arch = "riscv32")), ++ target_arch = "riscv32", ++ target_arch = "loongarch64")), + repr(align(8)))] + pub struct pthread_mutexattr_t { + #[doc(hidden)] +diff --git a/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/align.rs b/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/align.rs +new file mode 100644 +index 000000000..7ca870fd0 +--- /dev/null ++++ b/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/align.rs +@@ -0,0 +1,7 @@ ++s_no_extra_traits! { ++ #[allow(missing_debug_implementations)] ++ #[repr(align(16))] ++ pub struct max_align_t { ++ priv_: [f64; 4] ++ } ++} +diff --git a/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/mod.rs b/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/mod.rs +new file mode 100644 +index 000000000..25486cc3c +--- /dev/null ++++ b/vendor/libc/src/unix/linux_like/linux/gnu/b64/loongarch64/mod.rs +@@ -0,0 +1,932 @@ ++use pthread_mutex_t; ++ ++pub type c_char = i8; ++pub type c_long = i64; ++pub type c_ulong = u64; ++pub type wchar_t = i32; ++ ++pub type blksize_t = i32; ++pub type nlink_t = u32; ++pub type suseconds_t = i64; ++pub type __u64 = ::c_ulonglong; ++ ++s! { ++ pub struct stat { ++ pub st_dev: ::dev_t, ++ pub st_ino: ::ino_t, ++ pub st_mode: ::mode_t, ++ pub st_nlink: ::nlink_t, ++ pub st_uid: ::uid_t, ++ pub st_gid: ::gid_t, ++ pub st_rdev: ::dev_t, ++ __pad1: ::dev_t, ++ pub st_size: ::off_t, ++ pub st_blksize: ::blksize_t, ++ __pad2: ::c_int, ++ pub st_blocks: ::blkcnt_t, ++ pub st_atime: ::time_t, ++ pub st_atime_nsec: ::c_long, ++ pub st_mtime: ::time_t, ++ pub st_mtime_nsec: ::c_long, ++ pub st_ctime: ::time_t, ++ pub st_ctime_nsec: ::c_long, ++ __unused: [::c_int; 2], ++ } ++ ++ pub struct stat64 { ++ pub st_dev: ::dev_t, ++ pub st_ino: ::ino64_t, ++ pub st_mode: ::mode_t, ++ pub st_nlink: ::nlink_t, ++ pub st_uid: ::uid_t, ++ pub st_gid: ::gid_t, ++ pub st_rdev: ::dev_t, ++ pub __pad1: ::dev_t, ++ pub st_size: ::off64_t, ++ pub st_blksize: ::blksize_t, ++ pub __pad2: ::c_int, ++ pub st_blocks: ::blkcnt_t, ++ pub st_atime: ::time_t, ++ pub st_atime_nsec: ::c_long, ++ pub st_mtime: ::time_t, ++ pub st_mtime_nsec: ::c_long, ++ pub st_ctime: ::time_t, ++ pub st_ctime_nsec: ::c_long, ++ __unused: [::c_int; 2], ++ } ++ ++ pub struct statfs { ++ pub f_type: ::__fsword_t, ++ pub f_bsize: ::__fsword_t, ++ pub f_blocks: ::fsblkcnt_t, ++ pub f_bfree: ::fsblkcnt_t, ++ pub f_bavail: ::fsblkcnt_t, ++ pub f_files: ::fsfilcnt_t, ++ pub f_ffree: ::fsfilcnt_t, ++ pub f_fsid: ::fsid_t, ++ pub f_namelen: ::__fsword_t, ++ pub f_frsize: ::__fsword_t, ++ pub f_flags: ::__fsword_t, ++ pub f_spare: [::__fsword_t; 4], ++ } ++ ++ pub struct statfs64 { ++ pub f_type: ::__fsword_t, ++ pub f_bsize: ::__fsword_t, ++ pub f_blocks: u64, ++ pub f_bfree: u64, ++ pub f_bavail: u64, ++ pub f_files: u64, ++ pub f_ffree: u64, ++ pub f_fsid: ::fsid_t, ++ pub f_namelen: ::__fsword_t, ++ pub f_frsize: ::__fsword_t, ++ pub f_flags: ::__fsword_t, ++ pub f_spare: [::__fsword_t; 4], ++ } ++ ++ pub struct flock { ++ pub l_type: ::c_short, ++ pub l_whence: ::c_short, ++ pub l_start: ::off_t, ++ pub l_len: ::off_t, ++ pub l_pid: ::pid_t, ++ } ++ ++ pub struct flock64 { ++ pub l_type: ::c_short, ++ pub l_whence: ::c_short, ++ pub l_start: ::off64_t, ++ pub l_len: ::off64_t, ++ pub l_pid: ::pid_t, ++ } ++ ++ pub struct statvfs { ++ pub f_bsize: ::c_ulong, ++ pub f_frsize: ::c_ulong, ++ pub f_blocks: ::fsblkcnt_t, ++ pub f_bfree: ::fsblkcnt_t, ++ pub f_bavail: ::fsblkcnt_t, ++ pub f_files: ::fsfilcnt_t, ++ pub f_ffree: ::fsfilcnt_t, ++ pub f_favail: ::fsfilcnt_t, ++ pub f_fsid: ::c_ulong, ++ pub f_flag: ::c_ulong, ++ pub f_namemax: ::c_ulong, ++ __f_spare: [::c_int; 6], ++ } ++ ++ pub struct statvfs64 { ++ pub f_bsize: ::c_ulong, ++ pub f_frsize: ::c_ulong, ++ pub f_blocks: u64, ++ pub f_bfree: u64, ++ pub f_bavail: u64, ++ pub f_files: u64, ++ pub f_ffree: u64, ++ pub f_favail: u64, ++ pub f_fsid: ::c_ulong, ++ pub f_flag: ::c_ulong, ++ pub f_namemax: ::c_ulong, ++ __f_spare: [::c_int; 6], ++ } ++ ++ pub struct pthread_attr_t { ++ __size: [::c_ulong; 7] ++ } ++ ++ pub struct sigaction { ++ pub sa_sigaction: ::sighandler_t, ++ pub sa_mask: ::sigset_t, ++ pub sa_flags: ::c_int, ++ pub sa_restorer: ::Option, ++ } ++ ++ pub struct stack_t { ++ pub ss_sp: *mut ::c_void, ++ pub ss_flags: ::c_int, ++ pub ss_size: ::size_t, ++ } ++ ++ pub struct siginfo_t { ++ pub si_signo: ::c_int, ++ pub si_errno: ::c_int, ++ pub si_code: ::c_int, ++ #[doc(hidden)] ++ #[deprecated( ++ since="0.2.54", ++ note="Please leave a comment on \ ++ https://github.com/rust-lang/libc/pull/1316 if you're using \ ++ this field" ++ )] ++ pub _pad: [::c_int; 29], ++ _align: [u64; 0], ++ } ++ ++ pub struct ipc_perm { ++ pub __key: ::key_t, ++ pub uid: ::uid_t, ++ pub gid: ::gid_t, ++ pub cuid: ::uid_t, ++ pub cgid: ::gid_t, ++ pub mode: ::c_uint, ++ pub __seq: ::c_ushort, ++ __pad2: ::c_ushort, ++ __unused1: ::c_ulong, ++ __unused2: ::c_ulong ++ } ++ ++ pub struct shmid_ds { ++ pub shm_perm: ::ipc_perm, ++ pub shm_segsz: ::size_t, ++ pub shm_atime: ::time_t, ++ pub shm_dtime: ::time_t, ++ pub shm_ctime: ::time_t, ++ pub shm_cpid: ::pid_t, ++ pub shm_lpid: ::pid_t, ++ pub shm_nattch: ::shmatt_t, ++ __unused4: ::c_ulong, ++ __unused5: ::c_ulong ++ } ++ ++ pub struct termios2 { ++ pub c_iflag: ::tcflag_t, ++ pub c_oflag: ::tcflag_t, ++ pub c_cflag: ::tcflag_t, ++ pub c_lflag: ::tcflag_t, ++ pub c_line: ::cc_t, ++ pub c_cc: [::cc_t; 19], ++ pub c_ispeed: ::speed_t, ++ pub c_ospeed: ::speed_t, ++ } ++} ++ ++pub const __SIZEOF_PTHREAD_CONDATTR_T: usize = 4; ++pub const __SIZEOF_PTHREAD_MUTEXATTR_T: usize = 4; ++pub const __SIZEOF_PTHREAD_MUTEX_T: usize = 40; ++pub const __SIZEOF_PTHREAD_RWLOCK_T: usize = 56; ++ ++align_const! { ++ #[cfg(target_endian = "little")] ++ pub const PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++ #[cfg(target_endian = "little")] ++ pub const PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++ #[cfg(target_endian = "little")] ++ pub const PTHREAD_ADAPTIVE_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++ #[cfg(target_endian = "big")] ++ pub const PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++ #[cfg(target_endian = "big")] ++ pub const PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++ #[cfg(target_endian = "big")] ++ pub const PTHREAD_ADAPTIVE_MUTEX_INITIALIZER_NP: ::pthread_mutex_t = ++ pthread_mutex_t { ++ size: [ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ ], ++ }; ++} ++ ++pub const SYS_io_setup: ::c_long = 0; ++pub const SYS_io_destroy: ::c_long = 1; ++pub const SYS_io_submit: ::c_long = 2; ++pub const SYS_io_cancel: ::c_long = 3; ++pub const SYS_io_getevents: ::c_long = 4; ++pub const SYS_setxattr: ::c_long = 5; ++pub const SYS_lsetxattr: ::c_long = 6; ++pub const SYS_fsetxattr: ::c_long = 7; ++pub const SYS_getxattr: ::c_long = 8; ++pub const SYS_lgetxattr: ::c_long = 9; ++pub const SYS_fgetxattr: ::c_long = 10; ++pub const SYS_listxattr: ::c_long = 11; ++pub const SYS_llistxattr: ::c_long = 12; ++pub const SYS_flistxattr: ::c_long = 13; ++pub const SYS_removexattr: ::c_long = 14; ++pub const SYS_lremovexattr: ::c_long = 15; ++pub const SYS_fremovexattr: ::c_long = 16; ++pub const SYS_getcwd: ::c_long = 17; ++pub const SYS_lookup_dcookie: ::c_long = 18; ++pub const SYS_eventfd2: ::c_long = 19; ++pub const SYS_epoll_create1: ::c_long = 20; ++pub const SYS_epoll_ctl: ::c_long = 21; ++pub const SYS_epoll_pwait: ::c_long = 22; ++pub const SYS_dup: ::c_long = 23; ++pub const SYS_dup3: ::c_long = 24; ++pub const SYS_fcntl: ::c_long = 25; ++pub const SYS_fcntl64: ::c_long = 25; ++pub const SYS_inotify_init1: ::c_long = 26; ++pub const SYS_inotify_add_watch: ::c_long = 27; ++pub const SYS_inotify_rm_watch: ::c_long = 28; ++pub const SYS_ioctl: ::c_long = 29; ++pub const SYS_ioprio_set: ::c_long = 30; ++pub const SYS_ioprio_get: ::c_long = 31; ++pub const SYS_flock: ::c_long = 32; ++pub const SYS_mknodat: ::c_long = 33; ++pub const SYS_mkdirat: ::c_long = 34; ++pub const SYS_unlinkat: ::c_long = 35; ++pub const SYS_symlinkat: ::c_long = 36; ++pub const SYS_linkat: ::c_long = 37; ++pub const SYS_renameat: ::c_long = 38; ++pub const SYS_umount2: ::c_long = 39; ++pub const SYS_mount: ::c_long = 40; ++pub const SYS_pivot_root: ::c_long = 41; ++pub const SYS_nfsservctl: ::c_long = 42; ++pub const SYS_statfs: ::c_long = 43; ++pub const SYS_fstatfs: ::c_long = 44; ++pub const SYS_fstatfs64: ::c_long = 44; ++pub const SYS_truncate: ::c_long = 45; ++pub const SYS_truncate64: ::c_long = 45; ++pub const SYS_ftruncate: ::c_long = 46; ++pub const SYS_ftruncate64: ::c_long = 46; ++pub const SYS_fallocate: ::c_long = 47; ++pub const SYS_faccessat: ::c_long = 48; ++pub const SYS_chdir: ::c_long = 49; ++pub const SYS_fchdir: ::c_long = 50; ++pub const SYS_chroot: ::c_long = 51; ++pub const SYS_fchmod: ::c_long = 52; ++pub const SYS_fchmodat: ::c_long = 53; ++pub const SYS_fchownat: ::c_long = 54; ++pub const SYS_fchown: ::c_long = 55; ++pub const SYS_openat: ::c_long = 56; ++pub const SYS_close: ::c_long = 57; ++pub const SYS_vhangup: ::c_long = 58; ++pub const SYS_pipe2: ::c_long = 59; ++pub const SYS_quotactl: ::c_long = 60; ++pub const SYS_getdents64: ::c_long = 61; ++pub const SYS_lseek: ::c_long = 62; ++pub const SYS_read: ::c_long = 63; ++pub const SYS_write: ::c_long = 64; ++pub const SYS_readv: ::c_long = 65; ++pub const SYS_writev: ::c_long = 66; ++pub const SYS_pread64: ::c_long = 67; ++pub const SYS_pwrite64: ::c_long = 68; ++pub const SYS_preadv: ::c_long = 69; ++pub const SYS_pwritev: ::c_long = 70; ++pub const SYS_sendfile: ::c_long = 71; ++pub const SYS_pselect6: ::c_long = 72; ++pub const SYS_ppoll: ::c_long = 73; ++pub const SYS_signalfd4: ::c_long = 74; ++pub const SYS_vmsplice: ::c_long = 75; ++pub const SYS_splice: ::c_long = 76; ++pub const SYS_tee: ::c_long = 77; ++pub const SYS_readlinkat: ::c_long = 78; ++pub const SYS_newfstatat: ::c_long = 79; ++pub const SYS_fstat: ::c_long = 80; ++pub const SYS_fstat64: ::c_long = 80; ++pub const SYS_sync: ::c_long = 81; ++pub const SYS_fsync: ::c_long = 82; ++pub const SYS_fdatasync: ::c_long = 83; ++pub const SYS_sync_file_range2: ::c_long = 84; ++pub const SYS_sync_file_range: ::c_long = 84; ++pub const SYS_timerfd_create: ::c_long = 85; ++pub const SYS_timerfd_settime: ::c_long = 86; ++pub const SYS_timerfd_gettime: ::c_long = 87; ++pub const SYS_utimensat: ::c_long = 88; ++pub const SYS_acct: ::c_long = 89; ++pub const SYS_capget: ::c_long = 90; ++pub const SYS_capset: ::c_long = 91; ++pub const SYS_personality: ::c_long = 92; ++pub const SYS_exit: ::c_long = 93; ++pub const SYS_exit_group: ::c_long = 94; ++pub const SYS_waitid: ::c_long = 95; ++pub const SYS_set_tid_address: ::c_long = 96; ++pub const SYS_unshare: ::c_long = 97; ++pub const SYS_futex: ::c_long = 98; ++pub const SYS_set_robust_list: ::c_long = 99; ++pub const SYS_get_robust_list: ::c_long = 100; ++pub const SYS_nanosleep: ::c_long = 101; ++pub const SYS_getitimer: ::c_long = 102; ++pub const SYS_setitimer: ::c_long = 103; ++pub const SYS_kexec_load: ::c_long = 104; ++pub const SYS_init_module: ::c_long = 105; ++pub const SYS_delete_module: ::c_long = 106; ++pub const SYS_timer_create: ::c_long = 107; ++pub const SYS_timer_gettime: ::c_long = 108; ++pub const SYS_timer_getoverrun: ::c_long = 109; ++pub const SYS_timer_settime: ::c_long = 110; ++pub const SYS_timer_delete: ::c_long = 111; ++pub const SYS_clock_settime: ::c_long = 112; ++pub const SYS_clock_gettime: ::c_long = 113; ++pub const SYS_clock_getres: ::c_long = 114; ++pub const SYS_clock_nanosleep: ::c_long = 115; ++pub const SYS_syslog: ::c_long = 116; ++pub const SYS_ptrace: ::c_long = 117; ++pub const SYS_sched_setparam: ::c_long = 118; ++pub const SYS_sched_setscheduler: ::c_long = 119; ++pub const SYS_sched_getscheduler: ::c_long = 120; ++pub const SYS_sched_getparam: ::c_long = 121; ++pub const SYS_sched_setaffinity: ::c_long = 122; ++pub const SYS_sched_getaffinity: ::c_long = 123; ++pub const SYS_sched_yield: ::c_long = 124; ++pub const SYS_sched_get_priority_max: ::c_long = 125; ++pub const SYS_sched_get_priority_min: ::c_long = 126; ++pub const SYS_sched_rr_get_interval: ::c_long = 127; ++pub const SYS_restart_syscall: ::c_long = 128; ++pub const SYS_kill: ::c_long = 129; ++pub const SYS_tkill: ::c_long = 130; ++pub const SYS_tgkill: ::c_long = 131; ++pub const SYS_sigaltstack: ::c_long = 132; ++pub const SYS_rt_sigsuspend: ::c_long = 133; ++pub const SYS_rt_sigaction: ::c_long = 134; ++pub const SYS_rt_sigprocmask: ::c_long = 135; ++pub const SYS_rt_sigpending: ::c_long = 136; ++pub const SYS_rt_sigtimedwait: ::c_long = 137; ++pub const SYS_rt_sigqueueinfo: ::c_long = 138; ++pub const SYS_rt_sigreturn: ::c_long = 139; ++pub const SYS_setpriority: ::c_long = 140; ++pub const SYS_getpriority: ::c_long = 141; ++pub const SYS_reboot: ::c_long = 142; ++pub const SYS_setregid: ::c_long = 143; ++pub const SYS_setgid: ::c_long = 144; ++pub const SYS_setreuid: ::c_long = 145; ++pub const SYS_setuid: ::c_long = 146; ++pub const SYS_setresuid: ::c_long = 147; ++pub const SYS_getresuid: ::c_long = 148; ++pub const SYS_setresgid: ::c_long = 149; ++pub const SYS_getresgid: ::c_long = 150; ++pub const SYS_setfsuid: ::c_long = 151; ++pub const SYS_setfsgid: ::c_long = 152; ++pub const SYS_times: ::c_long = 153; ++pub const SYS_setpgid: ::c_long = 154; ++pub const SYS_getpgid: ::c_long = 155; ++pub const SYS_getsid: ::c_long = 156; ++pub const SYS_setsid: ::c_long = 157; ++pub const SYS_getgroups: ::c_long = 158; ++pub const SYS_setgroups: ::c_long = 159; ++pub const SYS_uname: ::c_long = 160; ++pub const SYS_sethostname: ::c_long = 161; ++pub const SYS_setdomainname: ::c_long = 162; ++pub const SYS_getrlimit: ::c_long = 163; ++pub const SYS_setrlimit: ::c_long = 164; ++pub const SYS_getrusage: ::c_long = 165; ++pub const SYS_umask: ::c_long = 166; ++pub const SYS_prctl: ::c_long = 167; ++pub const SYS_getcpu: ::c_long = 168; ++pub const SYS_gettimeofday: ::c_long = 169; ++pub const SYS_settimeofday: ::c_long = 170; ++pub const SYS_adjtimex: ::c_long = 171; ++pub const SYS_getpid: ::c_long = 172; ++pub const SYS_getppid: ::c_long = 173; ++pub const SYS_getuid: ::c_long = 174; ++pub const SYS_geteuid: ::c_long = 175; ++pub const SYS_getgid: ::c_long = 176; ++pub const SYS_getegid: ::c_long = 177; ++pub const SYS_gettid: ::c_long = 178; ++pub const SYS_sysinfo: ::c_long = 179; ++pub const SYS_mq_open: ::c_long = 180; ++pub const SYS_mq_unlink: ::c_long = 181; ++pub const SYS_mq_timedsend: ::c_long = 182; ++pub const SYS_mq_timedreceive: ::c_long = 183; ++pub const SYS_mq_notify: ::c_long = 184; ++pub const SYS_mq_getsetattr: ::c_long = 185; ++pub const SYS_msgget: ::c_long = 186; ++pub const SYS_msgctl: ::c_long = 187; ++pub const SYS_msgrcv: ::c_long = 188; ++pub const SYS_msgsnd: ::c_long = 189; ++pub const SYS_semget: ::c_long = 190; ++pub const SYS_semctl: ::c_long = 191; ++pub const SYS_semtimedop: ::c_long = 192; ++pub const SYS_semop: ::c_long = 193; ++pub const SYS_shmget: ::c_long = 194; ++pub const SYS_shmctl: ::c_long = 195; ++pub const SYS_shmat: ::c_long = 196; ++pub const SYS_shmdt: ::c_long = 197; ++pub const SYS_socket: ::c_long = 198; ++pub const SYS_socketpair: ::c_long = 199; ++pub const SYS_bind: ::c_long = 200; ++pub const SYS_listen: ::c_long = 201; ++pub const SYS_accept: ::c_long = 202; ++pub const SYS_connect: ::c_long = 203; ++pub const SYS_getsockname: ::c_long = 204; ++pub const SYS_getpeername: ::c_long = 205; ++pub const SYS_sendto: ::c_long = 206; ++pub const SYS_recvfrom: ::c_long = 207; ++pub const SYS_setsockopt: ::c_long = 208; ++pub const SYS_getsockopt: ::c_long = 209; ++pub const SYS_shutdown: ::c_long = 210; ++pub const SYS_sendmsg: ::c_long = 211; ++pub const SYS_recvmsg: ::c_long = 212; ++pub const SYS_readahead: ::c_long = 213; ++pub const SYS_brk: ::c_long = 214; ++pub const SYS_munmap: ::c_long = 215; ++pub const SYS_mremap: ::c_long = 216; ++pub const SYS_add_key: ::c_long = 217; ++pub const SYS_request_key: ::c_long = 218; ++pub const SYS_keyctl: ::c_long = 219; ++pub const SYS_clone: ::c_long = 220; ++pub const SYS_execve: ::c_long = 221; ++pub const SYS_mmap: ::c_long = 222; ++pub const SYS_mmap2: ::c_long = 222; ++pub const SYS_fadvise64: ::c_long = 223; ++pub const SYS_swapon: ::c_long = 224; ++pub const SYS_swapoff: ::c_long = 225; ++pub const SYS_mprotect: ::c_long = 226; ++pub const SYS_msync: ::c_long = 227; ++pub const SYS_mlock: ::c_long = 228; ++pub const SYS_munlock: ::c_long = 229; ++pub const SYS_mlockall: ::c_long = 230; ++pub const SYS_munlockall: ::c_long = 231; ++pub const SYS_mincore: ::c_long = 232; ++pub const SYS_madvise: ::c_long = 233; ++pub const SYS_remap_file_pages: ::c_long = 234; ++pub const SYS_mbind: ::c_long = 235; ++pub const SYS_get_mempolicy: ::c_long = 236; ++pub const SYS_set_mempolicy: ::c_long = 237; ++pub const SYS_migrate_pages: ::c_long = 238; ++pub const SYS_move_pages: ::c_long = 239; ++pub const SYS_rt_tgsigqueueinfo: ::c_long = 240; ++pub const SYS_perf_event_open: ::c_long = 241; ++pub const SYS_accept4: ::c_long = 242; ++pub const SYS_recvmmsg: ::c_long = 243; ++pub const SYS_arch_specific_syscall: ::c_long = 244; ++pub const SYS_wait4: ::c_long = 260; ++pub const SYS_prlimit64: ::c_long = 261; ++pub const SYS_fanotify_init: ::c_long = 262; ++pub const SYS_fanotify_mark: ::c_long = 263; ++pub const SYS_name_to_handle_at: ::c_long = 264; ++pub const SYS_open_by_handle_at: ::c_long = 265; ++pub const SYS_clock_adjtime: ::c_long = 266; ++pub const SYS_syncfs: ::c_long = 267; ++pub const SYS_setns: ::c_long = 268; ++pub const SYS_sendmmsg: ::c_long = 269; ++pub const SYS_process_vm_readv: ::c_long = 270; ++pub const SYS_process_vm_writev: ::c_long = 271; ++pub const SYS_kcmp: ::c_long = 272; ++pub const SYS_finit_module: ::c_long = 273; ++pub const SYS_sched_setattr: ::c_long = 274; ++pub const SYS_sched_getattr: ::c_long = 275; ++pub const SYS_renameat2: ::c_long = 276; ++pub const SYS_seccomp: ::c_long = 277; ++pub const SYS_getrandom: ::c_long = 278; ++pub const SYS_memfd_create: ::c_long = 279; ++pub const SYS_bpf: ::c_long = 280; ++pub const SYS_execveat: ::c_long = 281; ++pub const SYS_userfaultfd: ::c_long = 282; ++pub const SYS_membarrier: ::c_long = 283; ++pub const SYS_mlock2: ::c_long = 284; ++pub const SYS_copy_file_range: ::c_long = 285; ++pub const SYS_preadv2: ::c_long = 286; ++pub const SYS_pwritev2: ::c_long = 287; ++pub const SYS_pkey_mprotect: ::c_long = 288; ++pub const SYS_pkey_alloc: ::c_long = 289; ++pub const SYS_pkey_free: ::c_long = 290; ++pub const SYS_statx: ::c_long = 291; ++pub const SYS_io_pgetevents: ::c_long =292; ++pub const SYS_rseq: ::c_long = 293; ++pub const SYS_syscalls: ::c_long = 294; ++ ++pub const SYS_pidfd_open: ::c_long = 434; ++pub const SYS_clone3: ::c_long = 435; ++ ++ ++pub const SFD_CLOEXEC: ::c_int = 0x080000; ++pub const NCCS: usize = 32; ++ ++pub const POSIX_FADV_DONTNEED: ::c_int = 4; ++pub const POSIX_FADV_NOREUSE: ::c_int = 5; ++ ++pub const O_TRUNC: ::c_int = 512; ++pub const O_NOATIME: ::c_int = 0o1000000; ++pub const O_CLOEXEC: ::c_int = 0x80000; ++pub const O_PATH: ::c_int = 0o10000000; ++pub const O_TMPFILE: ::c_int = 0o20000000 | O_DIRECTORY; ++ ++pub const EBFONT: ::c_int = 59; ++pub const ENOSTR: ::c_int = 60; ++pub const ENODATA: ::c_int = 61; ++pub const ETIME: ::c_int = 62; ++pub const ENOSR: ::c_int = 63; ++pub const ENONET: ::c_int = 64; ++pub const ENOPKG: ::c_int = 65; ++pub const EREMOTE: ::c_int = 66; ++pub const ENOLINK: ::c_int = 67; ++pub const EADV: ::c_int = 68; ++pub const ESRMNT: ::c_int = 69; ++pub const ECOMM: ::c_int = 70; ++pub const EPROTO: ::c_int = 71; ++pub const EDOTDOT: ::c_int = 73; ++ ++pub const SA_NODEFER: ::c_int = 0x40000000; ++pub const SA_RESETHAND: ::c_int = 0x80000000; ++pub const SA_RESTART: ::c_int = 0x10000000; ++pub const SA_NOCLDSTOP: ::c_int = 0x00000001; ++ ++pub const EPOLL_CLOEXEC: ::c_int = 0x80000; ++pub const EFD_CLOEXEC: ::c_int = 0x80000; ++ ++pub const O_DIRECT: ::c_int = 0x4000; ++pub const O_DIRECTORY: ::c_int = 0x10000; ++pub const O_NOFOLLOW: ::c_int = 0x20000; ++ ++pub const RLIMIT_NOFILE: ::__rlimit_resource_t = 7; ++pub const RLIMIT_AS: ::__rlimit_resource_t = 9; ++pub const RLIMIT_RSS: ::__rlimit_resource_t = 5; ++pub const RLIMIT_NPROC: ::__rlimit_resource_t = 6; ++pub const RLIMIT_MEMLOCK: ::__rlimit_resource_t = 8; ++ ++pub const O_APPEND: ::c_int = 1024; ++pub const O_CREAT: ::c_int = 64; ++pub const O_EXCL: ::c_int = 128; ++pub const O_NOCTTY: ::c_int = 256; ++pub const O_NONBLOCK: ::c_int = 2048; ++pub const O_SYNC: ::c_int = 0x101000; ++pub const O_RSYNC: ::c_int = 0x101000; ++pub const O_FSYNC: ::c_int = 0x101000; ++pub const O_ASYNC: ::c_int = 0x2000; ++pub const O_DSYNC: ::c_int = 0x1000; ++pub const O_NDELAY: ::c_int = 0x800; ++ ++pub const EDEADLK: ::c_int = 35; ++pub const ENAMETOOLONG: ::c_int = 36; ++pub const ENOLCK: ::c_int = 37; ++pub const ENOSYS: ::c_int = 38; ++pub const ENOTEMPTY: ::c_int = 39; ++pub const ELOOP: ::c_int = 40; ++pub const ENOMSG: ::c_int = 42; ++pub const EIDRM: ::c_int = 43; ++pub const ECHRNG: ::c_int = 44; ++pub const EL2NSYNC: ::c_int = 45; ++pub const EL3HLT: ::c_int = 46; ++pub const EL3RST: ::c_int = 47; ++pub const ELNRNG: ::c_int = 48; ++pub const EUNATCH: ::c_int = 49; ++pub const ENOCSI: ::c_int = 50; ++pub const EL2HLT: ::c_int = 51; ++pub const EBADE: ::c_int = 52; ++pub const EBADR: ::c_int = 53; ++pub const EXFULL: ::c_int = 54; ++pub const ENOANO: ::c_int = 55; ++pub const EBADRQC: ::c_int = 56; ++pub const EBADSLT: ::c_int = 57; ++pub const EDEADLOCK: ::c_int = 35; ++pub const EMULTIHOP: ::c_int = 72; ++pub const EOVERFLOW: ::c_int = 75; ++pub const ENOTUNIQ: ::c_int = 76; ++pub const EBADFD: ::c_int = 77; ++pub const EBADMSG: ::c_int = 74; ++pub const EREMCHG: ::c_int = 78; ++pub const ELIBACC: ::c_int = 79; ++pub const ELIBBAD: ::c_int = 80; ++pub const ELIBSCN: ::c_int = 81; ++pub const ELIBMAX: ::c_int = 82; ++pub const ELIBEXEC: ::c_int = 83; ++pub const EILSEQ: ::c_int = 84; ++pub const ERESTART: ::c_int = 85; ++pub const ESTRPIPE: ::c_int = 86; ++pub const EUSERS: ::c_int = 87; ++pub const ENOTSOCK: ::c_int = 88; ++pub const EDESTADDRREQ: ::c_int = 89; ++pub const EMSGSIZE: ::c_int = 90; ++pub const EPROTOTYPE: ::c_int = 91; ++pub const ENOPROTOOPT: ::c_int = 92; ++pub const EPROTONOSUPPORT: ::c_int = 93; ++pub const ESOCKTNOSUPPORT: ::c_int = 94; ++pub const EOPNOTSUPP: ::c_int = 95; ++pub const EPFNOSUPPORT: ::c_int = 96; ++pub const EAFNOSUPPORT: ::c_int = 97; ++pub const EADDRINUSE: ::c_int = 98; ++pub const EADDRNOTAVAIL: ::c_int = 99; ++pub const ENETDOWN: ::c_int = 100; ++pub const ENETUNREACH: ::c_int = 101; ++pub const ENETRESET: ::c_int = 102; ++pub const ECONNABORTED: ::c_int = 103; ++pub const ECONNRESET: ::c_int = 104; ++pub const ENOBUFS: ::c_int = 105; ++pub const EISCONN: ::c_int = 106; ++pub const ENOTCONN: ::c_int = 107; ++pub const ESHUTDOWN: ::c_int = 108; ++pub const ETOOMANYREFS: ::c_int = 109; ++pub const ETIMEDOUT: ::c_int = 110; ++pub const ECONNREFUSED: ::c_int = 111; ++pub const EHOSTDOWN: ::c_int = 112; ++pub const EHOSTUNREACH: ::c_int = 113; ++pub const EALREADY: ::c_int = 114; ++pub const EINPROGRESS: ::c_int = 115; ++pub const ESTALE: ::c_int = 116; ++pub const EUCLEAN: ::c_int = 117; ++pub const ENOTNAM: ::c_int = 118; ++pub const ENAVAIL: ::c_int = 119; ++pub const EISNAM: ::c_int = 120; ++pub const EREMOTEIO: ::c_int = 121; ++pub const EDQUOT: ::c_int = 122; ++pub const ENOMEDIUM: ::c_int = 123; ++pub const EMEDIUMTYPE: ::c_int = 124; ++pub const ECANCELED: ::c_int = 125; ++pub const ENOKEY: ::c_int = 126; ++pub const EKEYEXPIRED: ::c_int = 127; ++pub const EKEYREVOKED: ::c_int = 128; ++pub const EKEYREJECTED: ::c_int = 129; ++pub const EOWNERDEAD: ::c_int = 130; ++pub const ENOTRECOVERABLE: ::c_int = 131; ++pub const ERFKILL: ::c_int = 132; ++pub const EHWPOISON: ::c_int = 133; ++ ++pub const MAP_NORESERVE: ::c_int = 0x4000; ++pub const MAP_ANONYMOUS: ::c_int = 0x0020; ++pub const MAP_ANON: ::c_int = 0x0020; ++pub const MAP_GROWSDOWN: ::c_int = 0x0100; ++pub const MAP_DENYWRITE: ::c_int = 0x0800; ++pub const MAP_EXECUTABLE: ::c_int = 0x1000; ++pub const MAP_LOCKED: ::c_int = 0x2000; ++pub const MAP_POPULATE: ::c_int = 0x8000; ++pub const MAP_NONBLOCK: ::c_int = 0x10000; ++pub const MAP_STACK: ::c_int = 0x20000; ++pub const MAP_HUGETLB: ::c_int = 0x40000; ++ ++pub const SOCK_STREAM: ::c_int = 1; ++pub const SOCK_DGRAM: ::c_int = 2; ++ ++pub const FIOCLEX: ::c_ulong = 0x5451; ++pub const FIONCLEX: ::c_ulong = 0x5450; ++pub const FIONBIO: ::c_ulong = 0x5421; ++ ++pub const SA_ONSTACK: ::c_int = 0x08000000; ++pub const SA_SIGINFO: ::c_int = 0x00000004; ++pub const SA_NOCLDWAIT: ::c_int = 0x00000002; ++ ++pub const SIGCHLD: ::c_int = 17; ++pub const SIGBUS: ::c_int = 7; ++pub const SIGTTIN: ::c_int = 21; ++pub const SIGTTOU: ::c_int = 22; ++pub const SIGXCPU: ::c_int = 24; ++pub const SIGXFSZ: ::c_int = 25; ++pub const SIGVTALRM: ::c_int = 26; ++pub const SIGPROF: ::c_int = 27; ++pub const SIGWINCH: ::c_int = 28; ++pub const SIGUSR1: ::c_int = 10; ++pub const SIGUSR2: ::c_int = 12; ++pub const SIGCONT: ::c_int = 18; ++pub const SIGSTOP: ::c_int = 19; ++pub const SIGTSTP: ::c_int = 20; ++pub const SIGURG: ::c_int = 23; ++pub const SIGIO: ::c_int = 29; ++pub const SIGSYS: ::c_int = 31; ++pub const SIGPOLL: ::c_int = 29; ++pub const SIGPWR: ::c_int = 30; ++pub const SIG_SETMASK: ::c_int = 2; ++pub const SIG_BLOCK: ::c_int = 0; ++pub const SIG_UNBLOCK: ::c_int = 1; ++ ++pub const POLLWRNORM: ::c_short = 0x100; ++pub const POLLWRBAND: ::c_short = 0x200; ++ ++pub const VEOF: usize = 4; ++pub const VEOL: usize = 11; ++pub const VEOL2: usize = 16; ++pub const VMIN: usize = 6; ++pub const IEXTEN: ::tcflag_t = 0x00008000; ++pub const TOSTOP: ::tcflag_t = 0x00000100; ++pub const FLUSHO: ::tcflag_t = 0x00001000; ++pub const EXTPROC: ::tcflag_t = 0x00010000; ++pub const TCSANOW: ::c_int = 0; ++pub const TCSADRAIN: ::c_int = 1; ++pub const TCSAFLUSH: ::c_int = 2; ++ ++pub const PTRACE_GETFPREGS: ::c_uint = 14; ++pub const PTRACE_SETFPREGS: ::c_uint = 15; ++pub const PTRACE_DETACH: ::c_uint = 17; ++pub const PTRACE_GETFPXREGS: ::c_uint = 18; ++pub const PTRACE_SETFPXREGS: ::c_uint = 19; ++pub const PTRACE_GETREGS: ::c_uint = 12; ++pub const PTRACE_SETREGS: ::c_uint = 13; ++ ++pub const EFD_NONBLOCK: ::c_int = 0x800; ++ ++pub const F_RDLCK: ::c_int = 0; ++pub const F_WRLCK: ::c_int = 1; ++pub const F_UNLCK: ::c_int = 2; ++pub const F_GETLK: ::c_int = 5; ++pub const F_GETOWN: ::c_int = 9; ++pub const F_SETOWN: ::c_int = 8; ++pub const F_SETLK: ::c_int = 6; ++pub const F_SETLKW: ::c_int = 7; ++pub const F_OFD_GETLK: ::c_int = 36; ++pub const F_OFD_SETLK: ::c_int = 37; ++pub const F_OFD_SETLKW: ::c_int = 38; ++ ++pub const SFD_NONBLOCK: ::c_int = 0x800; ++ ++pub const TCGETS: ::c_ulong = 0x5401; ++pub const TCSETS: ::c_ulong = 0x5402; ++pub const TCSETSW: ::c_ulong = 0x5403; ++pub const TCSETSF: ::c_ulong = 0x5404; ++pub const TCGETA: ::c_ulong = 0x5405; ++pub const TCSETA: ::c_ulong = 0x5406; ++pub const TCSETAW: ::c_ulong = 0x5407; ++pub const TCSETAF: ::c_ulong = 0x5408; ++pub const TCSBRK: ::c_ulong = 0x5409; ++pub const TCXONC: ::c_ulong = 0x540a; ++pub const TCFLSH: ::c_ulong = 0x540b; ++pub const TIOCSBRK: ::c_ulong = 0x5427; ++pub const TIOCCBRK: ::c_ulong = 0x5428; ++pub const TIOCGSOFTCAR: ::c_ulong = 0x5419; ++pub const TIOCSSOFTCAR: ::c_ulong = 0x541a; ++pub const TIOCINQ: ::c_ulong = 0x541b; ++pub const TIOCLINUX: ::c_ulong = 0x541c; ++pub const TIOCGSERIAL: ::c_ulong = 0x541e; ++pub const TIOCEXCL: ::c_ulong = 0x540c; ++pub const TIOCNXCL: ::c_ulong = 0x540d; ++pub const TIOCSCTTY: ::c_ulong = 0x540e; ++pub const TIOCGPGRP: ::c_ulong = 0x540f; ++pub const TIOCSPGRP: ::c_ulong = 0x5410; ++pub const TIOCOUTQ: ::c_ulong = 0x5411; ++pub const TIOCSTI: ::c_ulong = 0x5412; ++pub const TIOCGWINSZ: ::c_ulong = 0x5413; ++pub const TIOCSWINSZ: ::c_ulong = 0x5414; ++pub const TIOCMGET: ::c_ulong = 0x5415; ++pub const TIOCMBIS: ::c_ulong = 0x5416; ++pub const TIOCMBIC: ::c_ulong = 0x5417; ++pub const TIOCMSET: ::c_ulong = 0x5418; ++pub const FIONREAD: ::c_ulong = 0x541b; ++pub const TIOCCONS: ::c_ulong = 0x541d; ++ ++pub const RTLD_DEEPBIND: ::c_int = 0x8; ++pub const RTLD_GLOBAL: ::c_int = 0x100; ++pub const RTLD_NOLOAD: ::c_int = 0x4; ++ ++pub const MCL_CURRENT: ::c_int = 0x0001; ++pub const MCL_FUTURE: ::c_int = 0x0002; ++ ++pub const SIGSTKSZ: ::size_t = 8192; ++pub const MINSIGSTKSZ: ::size_t = 2048; ++pub const CBAUD: ::tcflag_t = 0o0010017; ++pub const TAB1: ::tcflag_t = 0x00000800; ++pub const TAB2: ::tcflag_t = 0x00001000; ++pub const TAB3: ::tcflag_t = 0x00001800; ++pub const CR1: ::tcflag_t = 0x00000200; ++pub const CR2: ::tcflag_t = 0x00000400; ++pub const CR3: ::tcflag_t = 0x00000600; ++pub const FF1: ::tcflag_t = 0x00008000; ++pub const BS1: ::tcflag_t = 0x00002000; ++pub const VT1: ::tcflag_t = 0x00004000; ++pub const VWERASE: usize = 14; ++pub const VREPRINT: usize = 12; ++pub const VSUSP: usize = 10; ++pub const VSTART: usize = 8; ++pub const VSTOP: usize = 9; ++pub const VDISCARD: usize = 13; ++pub const VTIME: usize = 5; ++pub const IXON: ::tcflag_t = 0x00000400; ++pub const IXOFF: ::tcflag_t = 0x00001000; ++pub const ONLCR: ::tcflag_t = 0x4; ++pub const CSIZE: ::tcflag_t = 0x00000030; ++pub const CS6: ::tcflag_t = 0x00000010; ++pub const CS7: ::tcflag_t = 0x00000020; ++pub const CS8: ::tcflag_t = 0x00000030; ++pub const CSTOPB: ::tcflag_t = 0x00000040; ++pub const CREAD: ::tcflag_t = 0x00000080; ++pub const PARENB: ::tcflag_t = 0x00000100; ++pub const PARODD: ::tcflag_t = 0x00000200; ++pub const HUPCL: ::tcflag_t = 0x00000400; ++pub const CLOCAL: ::tcflag_t = 0x00000800; ++pub const ECHOKE: ::tcflag_t = 0x00000800; ++pub const ECHOE: ::tcflag_t = 0x00000010; ++pub const ECHOK: ::tcflag_t = 0x00000020; ++pub const ECHONL: ::tcflag_t = 0x00000040; ++pub const ECHOPRT: ::tcflag_t = 0x00000400; ++pub const ECHOCTL: ::tcflag_t = 0x00000200; ++pub const ISIG: ::tcflag_t = 0x00000001; ++pub const ICANON: ::tcflag_t = 0x00000002; ++pub const PENDIN: ::tcflag_t = 0x00004000; ++pub const NOFLSH: ::tcflag_t = 0x00000080; ++pub const CIBAUD: ::tcflag_t = 0o02003600000; ++pub const CBAUDEX: ::tcflag_t = 0o010000; ++pub const VSWTC: usize = 7; ++pub const OLCUC: ::tcflag_t = 0o000002; ++pub const NLDLY: ::tcflag_t = 0o000400; ++pub const CRDLY: ::tcflag_t = 0o003000; ++pub const TABDLY: ::tcflag_t = 0o014000; ++pub const BSDLY: ::tcflag_t = 0o020000; ++pub const FFDLY: ::tcflag_t = 0o100000; ++pub const VTDLY: ::tcflag_t = 0o040000; ++pub const XTABS: ::tcflag_t = 0o014000; ++ ++pub const B0: ::speed_t = 0o000000; ++pub const B50: ::speed_t = 0o000001; ++pub const B75: ::speed_t = 0o000002; ++pub const B110: ::speed_t = 0o000003; ++pub const B134: ::speed_t = 0o000004; ++pub const B150: ::speed_t = 0o000005; ++pub const B200: ::speed_t = 0o000006; ++pub const B300: ::speed_t = 0o000007; ++pub const B600: ::speed_t = 0o000010; ++pub const B1200: ::speed_t = 0o000011; ++pub const B1800: ::speed_t = 0o000012; ++pub const B2400: ::speed_t = 0o000013; ++pub const B4800: ::speed_t = 0o000014; ++pub const B9600: ::speed_t = 0o000015; ++pub const B19200: ::speed_t = 0o000016; ++pub const B38400: ::speed_t = 0o000017; ++pub const EXTA: ::speed_t = B19200; ++pub const EXTB: ::speed_t = B38400; ++pub const BOTHER: ::speed_t = 0o010000; ++pub const B57600: ::speed_t = 0o010001; ++pub const B115200: ::speed_t = 0o010002; ++pub const B230400: ::speed_t = 0o010003; ++pub const B460800: ::speed_t = 0o010004; ++pub const B500000: ::speed_t = 0o010005; ++pub const B576000: ::speed_t = 0o010006; ++pub const B921600: ::speed_t = 0o010007; ++pub const B1000000: ::speed_t = 0o010010; ++pub const B1152000: ::speed_t = 0o010011; ++pub const B1500000: ::speed_t = 0o010012; ++pub const B2000000: ::speed_t = 0o010013; ++pub const B2500000: ::speed_t = 0o010014; ++pub const B3000000: ::speed_t = 0o010015; ++pub const B3500000: ::speed_t = 0o010016; ++pub const B4000000: ::speed_t = 0o010017; ++ ++pub const TIOCM_ST: ::c_int = 0x008; ++pub const TIOCM_SR: ::c_int = 0x010; ++pub const TIOCM_CTS: ::c_int = 0x020; ++pub const TIOCM_CAR: ::c_int = 0x040; ++pub const TIOCM_RNG: ::c_int = 0x080; ++pub const TIOCM_DSR: ::c_int = 0x100; ++ ++extern "C" { ++ pub fn sysctl( ++ name: *mut ::c_int, ++ namelen: ::c_int, ++ oldp: *mut ::c_void, ++ oldlenp: *mut ::size_t, ++ newp: *mut ::c_void, ++ newlen: ::size_t, ++ ) -> ::c_int; ++} ++ ++cfg_if! { ++ if #[cfg(libc_align)] { ++ mod align; ++ pub use self::align::*; ++ } ++} +diff --git a/vendor/libc/src/unix/linux_like/linux/gnu/b64/mod.rs b/vendor/libc/src/unix/linux_like/linux/gnu/b64/mod.rs +index db82f26dc..2c3ded335 100644 +--- a/vendor/libc/src/unix/linux_like/linux/gnu/b64/mod.rs ++++ b/vendor/libc/src/unix/linux_like/linux/gnu/b64/mod.rs +@@ -70,6 +70,7 @@ s! { + pub sem_otime: ::time_t, + #[cfg(not(any( + target_arch = "aarch64", ++ target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "powerpc64", + target_arch = "riscv64", +@@ -78,6 +79,7 @@ s! { + pub sem_ctime: ::time_t, + #[cfg(not(any( + target_arch = "aarch64", ++ target_arch = "loongarch64", + target_arch = "mips64", + target_arch = "powerpc64", + target_arch = "riscv64", +@@ -116,6 +118,9 @@ cfg_if! { + } else if #[cfg(any(target_arch = "riscv64"))] { + mod riscv64; + pub use self::riscv64::*; ++ } else if #[cfg(any(target_arch = "loongarch64"))] { ++ mod loongarch64; ++ pub use self::loongarch64::*; + } else { + // Unknown target_arch + } +diff --git a/vendor/libc/src/unix/linux_like/linux/gnu/mod.rs b/vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +index bb2a777d7..92e09f682 100644 +--- a/vendor/libc/src/unix/linux_like/linux/gnu/mod.rs ++++ b/vendor/libc/src/unix/linux_like/linux/gnu/mod.rs +@@ -411,22 +411,26 @@ s_no_extra_traits! { + + #[cfg(any(target_arch = "aarch64", + target_arch = "s390x", ++ target_arch = "loongarch64", + all(target_pointer_width = "32", + not(target_arch = "x86_64"))))] + pub ut_session: ::c_long, + #[cfg(any(target_arch = "aarch64", + target_arch = "s390x", ++ target_arch = "loongarch64", + all(target_pointer_width = "32", + not(target_arch = "x86_64"))))] + pub ut_tv: ::timeval, + + #[cfg(not(any(target_arch = "aarch64", + target_arch = "s390x", ++ target_arch = "loongarch64", + all(target_pointer_width = "32", + not(target_arch = "x86_64")))))] + pub ut_session: i32, + #[cfg(not(any(target_arch = "aarch64", + target_arch = "s390x", ++ target_arch = "loongarch64", + all(target_pointer_width = "32", + not(target_arch = "x86_64")))))] + pub ut_tv: __timeval, +@@ -1336,7 +1340,8 @@ cfg_if! { + target_arch = "mips64", + target_arch = "s390x", + target_arch = "sparc64", +- target_arch = "riscv64"))] { ++ target_arch = "riscv64", ++ target_arch = "loongarch64"))] { + mod b64; + pub use self::b64::*; + } else { +diff --git a/vendor/libc/src/unix/linux_like/linux/no_align.rs b/vendor/libc/src/unix/linux_like/linux/no_align.rs +index de64be5a3..b64b1d4da 100644 +--- a/vendor/libc/src/unix/linux_like/linux/no_align.rs ++++ b/vendor/libc/src/unix/linux_like/linux/no_align.rs +@@ -9,6 +9,7 @@ macro_rules! expand_align { + target_arch = "sparc64", + target_arch = "riscv64", + target_arch = "riscv32", ++ target_arch = "loongarch64", + all(target_arch = "aarch64", + target_env = "musl")))] + __align: [::c_int; 0], +@@ -19,6 +20,7 @@ macro_rules! expand_align { + target_arch = "sparc64", + target_arch = "riscv64", + target_arch = "riscv32", ++ target_arch = "loongarch64", + all(target_arch = "aarch64", + target_env = "musl"))))] + __align: [::c_long; 0], +diff --git a/vendor/object/src/common.rs b/vendor/object/src/common.rs +index c86665c21..0759a9d4e 100644 +--- a/vendor/object/src/common.rs ++++ b/vendor/object/src/common.rs +@@ -23,6 +23,7 @@ pub enum Architecture { + S390x, + Sparc64, + Wasm32, ++ LoongArch64, + } + + impl Architecture { +@@ -50,6 +51,7 @@ impl Architecture { + Architecture::S390x => Some(AddressSize::U64), + Architecture::Sparc64 => Some(AddressSize::U64), + Architecture::Wasm32 => Some(AddressSize::U32), ++ Architecture::LoongArch64 => Some(AddressSize::U64), + } + } + } +diff --git a/vendor/object/src/elf.rs b/vendor/object/src/elf.rs +index 28ac16bbe..83510bcfe 100644 +--- a/vendor/object/src/elf.rs ++++ b/vendor/object/src/elf.rs +@@ -564,6 +564,8 @@ pub const EM_BPF: u16 = 247; + pub const EM_CSKY: u16 = 252; + /// Digital Alpha + pub const EM_ALPHA: u16 = 0x9026; ++/// LOONGARCH ++pub const EM_LOONGARCH: u16 = 258; + + // Values for `FileHeader*::e_version` and `Ident::version`. + /// Invalid ELF version. +@@ -6081,6 +6083,201 @@ pub const R_RISCV_SET32: u32 = 56; + #[allow(missing_docs)] + pub const R_RISCV_32_PCREL: u32 = 57; + ++// LoongArch values `FileHeader*::e_flags`. ++/// Uses 64-bit GPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_LP64S: u32 = 0x1; ++/// Uses 64-bit GPRs, 32-bit FPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_LP64F: u32 = 0x2; ++/// Uses 64-bit GPRs, 64-bit FPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_LP64D: u32 = 0x3; ++/// Uses 32-bit GPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_ILP32S: u32 = 0x5; ++/// Uses 32-bit GPRs, 32-bit FPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_ILP32F: u32 = 0x6; ++/// Uses 32-bit GPRs, 64-bit FPRs and the stack for parameter passing ++pub const EF_LARCH_ABI_ILP32D: u32 = 0x7; ++ ++// LOONGARCH values `Rel*::r_type`. ++/* Loongarch specific dynamic relocations. */ ++#[allow(missing_docs)] ++pub const R_LARCH_NONE: u32 = 0; ++#[allow(missing_docs)] ++pub const R_LARCH_32: u32 = 1; ++#[allow(missing_docs)] ++pub const R_LARCH_64: u32 = 2; ++#[allow(missing_docs)] ++pub const R_LARCH_RELATIVE: u32 = 3; ++#[allow(missing_docs)] ++pub const R_LARCH_COPY: u32 = 4; ++#[allow(missing_docs)] ++pub const R_LARCH_JUMP_SLOT: u32 = 5; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_DTPMOD32: u32 = 6; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_DTPMOD64: u32 = 7; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_DTPREL32: u32 = 8; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_DTPREL64: u32 = 9; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_TPREL32: u32 = 10; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_TPREL64: u32 = 11; ++#[allow(missing_docs)] ++pub const R_LARCH_IRELATIVE: u32 = 12; ++#[allow(missing_docs)] ++pub const R_LARCH_MARK_LA: u32 = 20; ++#[allow(missing_docs)] ++pub const R_LARCH_MARK_PCREL: u32 = 21; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_PCREL: u32 = 22; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_ABSOLUTE: u32 = 23; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_DUP: u32 = 24; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_GPREL: u32 = 25; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_TLS_TPREL: u32 = 26; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_TLS_GOT: u32 = 27; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_TLS_GD: u32 = 28; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_PUSH_PLT_PCREL: u32 = 29; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_ASSERT: u32 = 30; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_NOT: u32 = 31; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_SUB: u32 = 32; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_SL: u32 = 33; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_SR: u32 = 34; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_ADD: u32 = 35; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_AND: u32 = 36; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_IF_ELSE: u32 = 37; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_10_5: u32 = 38; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_U_10_12: u32 = 39; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_10_12: u32 = 40; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_10_16: u32 = 41; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_10_16_S2: u32 = 42; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_5_20: u32 = 43; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_0_5_10_16_S2: u32 = 44; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_S_0_10_10_16_S2: u32 = 45; ++#[allow(missing_docs)] ++pub const R_LARCH_SOP_POP_32_U: u32 = 46; ++#[allow(missing_docs)] ++pub const R_LARCH_ADD8: u32 = 47; ++#[allow(missing_docs)] ++pub const R_LARCH_ADD16: u32 = 48; ++#[allow(missing_docs)] ++pub const R_LARCH_ADD24: u32 = 49; ++#[allow(missing_docs)] ++pub const R_LARCH_ADD32: u32 = 50; ++#[allow(missing_docs)] ++pub const R_LARCH_ADD64: u32 = 51; ++#[allow(missing_docs)] ++pub const R_LARCH_SUB8: u32 = 52; ++#[allow(missing_docs)] ++pub const R_LARCH_SUB16: u32 = 53; ++#[allow(missing_docs)] ++pub const R_LARCH_SUB24: u32 = 54; ++#[allow(missing_docs)] ++pub const R_LARCH_SUB32: u32 = 55; ++#[allow(missing_docs)] ++pub const R_LARCH_SUB64: u32 = 56; ++#[allow(missing_docs)] ++pub const R_LARCH_GNU_VTINHERIT: u32 = 57; ++#[allow(missing_docs)] ++pub const R_LARCH_GNU_VTENTRY: u32 = 58; ++#[allow(missing_docs)] ++pub const R_LARCH_B16: u32 = 64; ++#[allow(missing_docs)] ++pub const R_LARCH_B21: u32 = 65; ++#[allow(missing_docs)] ++pub const R_LARCH_B26: u32 = 66; ++#[allow(missing_docs)] ++pub const R_LARCH_ABS_HI20: u32 = 67; ++#[allow(missing_docs)] ++pub const R_LARCH_ABS_LO12: u32 = 68; ++#[allow(missing_docs)] ++pub const R_LARCH_ABS64_LO20: u32 = 69; ++#[allow(missing_docs)] ++pub const R_LARCH_ABS64_HI12: u32 = 70; ++#[allow(missing_docs)] ++pub const R_LARCH_PCALA_HI20: u32 = 71; ++#[allow(missing_docs)] ++pub const R_LARCH_PCALA_LO12: u32 = 72; ++#[allow(missing_docs)] ++pub const R_LARCH_PCALA64_LO20: u32 = 73; ++#[allow(missing_docs)] ++pub const R_LARCH_PCALA64_HI12: u32 = 74; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT_PC_HI20: u32 = 75; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT_PC_LO12: u32 = 76; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT64_PC_LO20: u32 = 77; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT64_PC_HI12: u32 = 78; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT_HI20: u32 = 79; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT_LO12: u32 = 80; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT64_LO20: u32 = 81; ++#[allow(missing_docs)] ++pub const R_LARCH_GOT64_HI12: u32 = 82; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LE_HI20: u32 = 83; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LE_LO12: u32 = 84; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LE64_LO20: u32 = 85; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LE64_HI12: u32 = 86; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE_PC_HI20: u32 = 87; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE_PC_LO12: u32 = 88; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE64_PC_LO20: u32 = 89; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE64_PC_HI12: u32 = 90; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE_HI20: u32 = 91; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE_LO12: u32 = 92; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE64_LO20: u32 = 93; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_IE64_HI12: u32 = 94; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LD_PC_HI20: u32 = 95; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_LD_HI20: u32 = 96; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_GD_PC_HI20: u32 = 97; ++#[allow(missing_docs)] ++pub const R_LARCH_TLS_GD_HI20: u32 = 98; ++#[allow(missing_docs)] ++pub const R_LARCH_32_PCREL: u32 = 99; ++#[allow(missing_docs)] ++pub const R_LARCH_RELAX: u32 = 100; ++ + // BPF values `Rel*::r_type`. + /// No reloc + pub const R_BPF_NONE: u32 = 0; +diff --git a/vendor/object/src/read/elf/file.rs b/vendor/object/src/read/elf/file.rs +index 91273ca41..5340a8ed1 100644 +--- a/vendor/object/src/read/elf/file.rs ++++ b/vendor/object/src/read/elf/file.rs +@@ -172,6 +172,7 @@ where + // We only support the 64-bit variant s390x here. + (elf::EM_S390, true) => Architecture::S390x, + (elf::EM_SPARCV9, true) => Architecture::Sparc64, ++ (elf::EM_LOONGARCH, true) => Architecture::LoongArch64, + _ => Architecture::Unknown, + } + } +diff --git a/vendor/object/src/read/elf/relocation.rs b/vendor/object/src/read/elf/relocation.rs +index d3e24b2e8..6ce97b945 100644 +--- a/vendor/object/src/read/elf/relocation.rs ++++ b/vendor/object/src/read/elf/relocation.rs +@@ -373,6 +373,11 @@ fn parse_relocation( + elf::R_SPARC_64 | elf::R_SPARC_UA64 => (RelocationKind::Absolute, 64), + r_type => (RelocationKind::Elf(r_type), 0), + } ++ }, ++ elf::EM_LOONGARCH => match reloc.r_type(endian, false) { ++ elf::R_LARCH_32 => (RelocationKind::Absolute, 32), ++ elf::R_LARCH_64 => (RelocationKind::Absolute, 64), ++ r_type => (RelocationKind::Elf(r_type), 0), + } + _ => (RelocationKind::Elf(reloc.r_type(endian, false)), 0), + }; +diff --git a/vendor/object/src/write/elf.rs b/vendor/object/src/write/elf.rs +index 34e0abc85..3d208f2dd 100644 +--- a/vendor/object/src/write/elf.rs ++++ b/vendor/object/src/write/elf.rs +@@ -88,6 +88,7 @@ impl Object { + Architecture::Riscv32 => true, + Architecture::S390x => true, + Architecture::Sparc64 => true, ++ Architecture::LoongArch64 => true, + _ => { + return Err(Error(format!( + "unimplemented architecture {:?}", +@@ -371,6 +372,7 @@ impl Object { + Architecture::Riscv64 => elf::EM_RISCV, + Architecture::S390x => elf::EM_S390, + Architecture::Sparc64 => elf::EM_SPARCV9, ++ Architecture::LoongArch64 => elf::EM_LOONGARCH, + _ => { + return Err(Error(format!( + "unimplemented architecture {:?}", +@@ -807,6 +809,14 @@ impl Object { + return Err(Error(format!("unimplemented relocation {:?}", reloc))); + } + }, ++ Architecture::LoongArch64 => match (reloc.kind, reloc.encoding, reloc.size) { ++ (RelocationKind::Absolute, _, 32) => elf::R_LARCH_32, ++ (RelocationKind::Absolute, _, 64) => elf::R_LARCH_64, ++ (RelocationKind::Elf(x), _, _) => x, ++ _ => { ++ return Err(Error(format!("unimplemented relocation {:?}", reloc))); ++ } ++ }, + _ => { + if let RelocationKind::Elf(x) = reloc.kind { + x +diff --git a/vendor/object/tests/round_trip/mod.rs b/vendor/object/tests/round_trip/mod.rs +index 37050689f..a63722e01 100644 +--- a/vendor/object/tests/round_trip/mod.rs ++++ b/vendor/object/tests/round_trip/mod.rs +@@ -245,6 +245,7 @@ fn elf_any() { + (Architecture::Riscv64, Endianness::Little), + (Architecture::S390x, Endianness::Big), + (Architecture::Sparc64, Endianness::Big), ++ (Architecture::LoongArch64, Endianness::Little), + ] + .iter() + .copied() +diff --git a/vendor/psm/build.rs b/vendor/psm/build.rs +index 01a13bf71..da351b21f 100644 +--- a/vendor/psm/build.rs ++++ b/vendor/psm/build.rs +@@ -50,6 +50,7 @@ fn find_assembly( + ("sparc", _, _, _) => Some(("src/arch/sparc_sysv.s", true)), + ("riscv32", _, _, _) => Some(("src/arch/riscv.s", true)), + ("riscv64", _, _, _) => Some(("src/arch/riscv64.s", true)), ++ ("loongarch64", _, _, _) => Some(("src/arch/loongarch64.s", true)), + ("wasm32", _, _, _) => Some(("src/arch/wasm32.o", true)), + _ => None, + } +diff --git a/vendor/psm/src/arch/loongarch64.s b/vendor/psm/src/arch/loongarch64.s +new file mode 100644 +index 000000000..3fc654963 +--- /dev/null ++++ b/vendor/psm/src/arch/loongarch64.s +@@ -0,0 +1,63 @@ ++#include "psm.h" ++ ++.text ++.globl rust_psm_stack_direction ++.align 2 ++.type rust_psm_stack_direction,@function ++rust_psm_stack_direction: ++/* extern "C" fn() -> u8 */ ++.cfi_startproc ++ li.w $r4, STACK_DIRECTION_DESCENDING ++ jr $r1 ++.rust_psm_stack_direction_end: ++.size rust_psm_stack_direction,.rust_psm_stack_direction_end-rust_psm_stack_direction ++.cfi_endproc ++ ++ ++.globl rust_psm_stack_pointer ++.align 2 ++.type rust_psm_stack_pointer,@function ++rust_psm_stack_pointer: ++/* extern "C" fn() -> *mut u8 */ ++.cfi_startproc ++ move $r4, $r3 ++ jr $r1 ++.rust_psm_stack_pointer_end: ++.size rust_psm_stack_pointer,.rust_psm_stack_pointer_end-rust_psm_stack_pointer ++.cfi_endproc ++ ++ ++.globl rust_psm_replace_stack ++.align 2 ++.type rust_psm_replace_stack,@function ++rust_psm_replace_stack: ++/* extern "C" fn(r4: usize, r5: extern "C" fn(usize), r6: *mut u8) */ ++.cfi_startproc ++ move $r3, $r6 ++ jr $r5 ++.rust_psm_replace_stack_end: ++.size rust_psm_replace_stack,.rust_psm_replace_stack_end-rust_psm_replace_stack ++.cfi_endproc ++ ++ ++.globl rust_psm_on_stack ++.align 2 ++.type rust_psm_on_stack,@function ++rust_psm_on_stack: ++/* extern "C" fn(r4: usize, r5: usize, r6: extern "C" fn(usize, usize), r7: *mut u8) */ ++.cfi_startproc ++ st.d $r1, $r7, -8 ++ st.d $r3, $r7, -16 ++ addi.d $r3, $r7, -16 ++ .cfi_def_cfa 3, 16 ++ .cfi_offset 1, -8 ++ .cfi_offset 3, -16 ++ jirl $r1, $r6, 0 ++ ld.d $r1, $r3, 8 ++ .cfi_restore 1 ++ ld.d $r3, $r3, 0 ++ .cfi_restore 3 ++ jr $r1 ++.rust_psm_on_stack_end: ++.size rust_psm_on_stack,.rust_psm_on_stack_end-rust_psm_on_stack ++.cfi_endproc +-- +2.27.0 + diff --git a/rust.spec b/rust.spec index 6d2ba00a7c387f79c2133a0b62963b42ebe4e53c..96f0723faf7eb144fa9e6f8c16c7a23db8573d30 100644 --- a/rust.spec +++ b/rust.spec @@ -1,4 +1,4 @@ -%global rust_arches x86_64 i686 armv7hl aarch64 ppc64 ppc64le s390x +%global rust_arches x86_64 i686 armv7hl aarch64 ppc64 ppc64le s390x loongarch64 %{!?channel: %global channel stable} %global bootstrap_rust 1.56.0 %global bootstrap_cargo 1.56.0 @@ -12,7 +12,7 @@ %bcond_without lldb Name: rust Version: 1.57.0 -Release: 1 +Release: 2 Summary: The Rust Programming Language License: (ASL 2.0 or MIT) and (BSD and MIT) URL: https://www.rust-lang.org @@ -30,6 +30,8 @@ Patch0002: clippy-driver-usage-should-user-friendly.patch Patch0003: cargo-help-clippy-should-have-description-to-user.patch Patch0004: fix-a-println-wrong-format.patch Patch0005: remove-field-is-never-read-warning.patch +Patch0006: 0001-Add-loongarch64-support-for-rust-1.57.patch +Patch0007: 0002-vendor-Add-loongarch64-support.patch %{lua: function rust_triple(arch) local abi = "gnu" if arch == "armv7hl" then @@ -41,6 +43,8 @@ Patch0005: remove-field-is-never-read-warning.patch arch = "powerpc64le" elseif arch == "riscv64" then arch = "riscv64gc" + elseif arch == "loongarch64" then + return arch.."-unknown-linux-"..abi.."f64" end return arch.."-unknown-linux-"..abi end} @@ -52,8 +56,11 @@ end} return "--musl-root-"..arch end} %global rust_triple %{lua: print(rust_triple(rpm.expand("%{_target_cpu}")))} + +%ifnarch loongarch64 %global rust_musl_triple %{lua: print(rust_musl_triple(rpm.expand("%{_target_cpu}")))} %global rust_musl_root %{lua: print(rust_musl_root(rpm.expand("%{_target_cpu}")))} +%endif %if %defined bootstrap_arches %{lua: do local bootstrap_arches = {} @@ -251,6 +258,8 @@ sed -i.try-python -e '/^try python3 /i try "%{python}" "$@"' ./configure %patch0003 -p1 %patch0004 -p1 %patch0005 -p1 +%patch0006 -p1 +%patch0007 -p1 rm -rf vendor/curl-sys/curl/ rm -rf vendor/jemalloc-sys/jemalloc/ rm -rf vendor/libssh2-sys/libssh2/ @@ -303,7 +312,7 @@ fi %configure --disable-option-checking \ --libdir=%{common_libdir} \ %{rust_musl_root}=%{musl_root} \ - --build=%{rust_triple} --host=%{rust_triple} --target=%{rust_triple},%{rust_musl_triple} \ + --build=%{rust_triple} --host=%{rust_triple} --target=%{rust_triple},%{?rust_musl_triple} \ --python=%{python} \ --local-rust-root=%{local_rust_root} \ %{!?with_bundled_llvm: --llvm-root=%{llvm_root} \ @@ -466,6 +475,9 @@ export %{rust_env} %{_mandir}/man1/cargo*.1* %changelog +* Mon Sep 26 2022 yangxiaojuan - 1.57.0-2 +- Add loongarch64 support + * Mon Feb 14 2022 chenchen - 1.57.0-1 - Update to 1.57.0