diff --git a/Add-HWCAP_LOONGARCH_LSPW-from-Linux-6.12-to-bits-hwc.patch b/Add-HWCAP_LOONGARCH_LSPW-from-Linux-6.12-to-bits-hwc.patch new file mode 100644 index 0000000000000000000000000000000000000000..97144fede1866b59f0a24439fe9f75be487f33b1 --- /dev/null +++ b/Add-HWCAP_LOONGARCH_LSPW-from-Linux-6.12-to-bits-hwc.patch @@ -0,0 +1,25 @@ +From f8661bbdd3abe67c08d40ba88c6a9e02c0a51f25 Mon Sep 17 00:00:00 2001 +From: Joseph Myers +Date: Fri, 20 Dec 2024 11:47:03 +0000 +Subject: [PATCH 2/4] Add HWCAP_LOONGARCH_LSPW from Linux 6.12 to bits/hwcap.h + +Add the new Linux 6.12 HWCAP_LOONGARCH_LSPW to the corresponding +bits/hwcap.h. + +Tested with build-many-glibcs.py for loongarch64-linux-gnu-lp64d. +--- + sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h b/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h +index 7acec23d..fa9f4bd7 100644 +--- a/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h ++++ b/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h +@@ -36,3 +36,4 @@ + #define HWCAP_LOONGARCH_LBT_ARM (1 << 11) + #define HWCAP_LOONGARCH_LBT_MIPS (1 << 12) + #define HWCAP_LOONGARCH_PTW (1 << 13) ++#define HWCAP_LOONGARCH_LSPW (1 << 14) +-- +2.47.3 + diff --git a/LoongArch-Update-ulps.patch b/LoongArch-Update-ulps.patch new file mode 100644 index 0000000000000000000000000000000000000000..7c27ebdc8051e060587e78e22619a388305d5cc4 --- /dev/null +++ b/LoongArch-Update-ulps.patch @@ -0,0 +1,38 @@ +From c988fdee39681d2fc118126fe6ecc9704c1d704c Mon Sep 17 00:00:00 2001 +From: caiyinyu +Date: Mon, 11 Nov 2024 09:56:05 +0800 +Subject: [PATCH 1/4] LoongArch: Update ulps + +Needed for test-float-cacosh, test-float-csin, test-float32-cacosh and +test-float32-csin. + +Signed-off-by: caiyinyu +Reviewed-by: Florian Weimer +--- + sysdeps/loongarch/lp64/libm-test-ulps | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/sysdeps/loongarch/lp64/libm-test-ulps b/sysdeps/loongarch/lp64/libm-test-ulps +index 770bf36b..4ecc0e65 100644 +--- a/sysdeps/loongarch/lp64/libm-test-ulps ++++ b/sysdeps/loongarch/lp64/libm-test-ulps +@@ -228,7 +228,7 @@ ldouble: 3 + + Function: Real part of "cacosh_upward": + double: 4 +-float: 3 ++float: 4 + ldouble: 6 + + Function: Imaginary part of "cacosh_upward": +@@ -720,6 +720,7 @@ float: 1 + ldouble: 1 + + Function: Imaginary part of "csin": ++float: 1 + ldouble: 1 + + Function: Real part of "csin_downward": +-- +2.47.3 + diff --git a/backport-x86-Disable-AVX-Fast-Unaligned-Load-on-Hygon-1-2-3.patch b/backport-x86-Disable-AVX-Fast-Unaligned-Load-on-Hygon-1-2-3.patch new file mode 100644 index 0000000000000000000000000000000000000000..52c865ed7fb18babeb8c93f215b6b3a54e143f25 --- /dev/null +++ b/backport-x86-Disable-AVX-Fast-Unaligned-Load-on-Hygon-1-2-3.patch @@ -0,0 +1,40 @@ +From 00d406e77bb0e49d79dc1b13d7077436ee5cdf14 Mon Sep 17 00:00:00 2001 +From: litenglong +Date: Fri, 17 Oct 2025 09:45:41 +0800 +Subject: [PATCH] x86: Disable AVX Fast Unaligned Load on Hygon 1/2/3 + +- Performance testing revealed significant memcpy performance degradation + when bit_arch_AVX_Fast_Unaligned_Load is enabled on Hygon 3. +- Hygon confirmed AVX performance issues in certain memory functions. +- Glibc benchmarks show SSE outperforms AVX for + memcpy/memmove/memset/strcmp/strcpy/strlen and so on. +- Hardware differences primarily in floating-point operations don't justify + AVX usage for memory operations. + +Reviewed-by: gaoxiang +Signed-off-by: litenglong +Reviewed-by: H.J. Lu +--- + sysdeps/x86/cpu-features.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index b67ef541dd..c696a4d1f7 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -1123,6 +1123,12 @@ disable_tsx: + hardware. */ + cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] + &= ~bit_arch_Avoid_Non_Temporal_Memset; ++ if (model < 0x4) ++ { ++ /* Unaligned AVX loads are slower. */ ++ cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load] ++ &= ~bit_arch_AVX_Fast_Unaligned_Load; ++ } + } + else + { +-- +2.25.1 + diff --git a/glibc.spec b/glibc.spec index 00f6d22adf392f9ec1ba4f8b4c6f3526ccf9bda4..75f98389e5201f3f5f5c6a6b7830eef85a39c6fc 100644 --- a/glibc.spec +++ b/glibc.spec @@ -67,7 +67,7 @@ ############################################################################## Name: glibc Version: 2.38 -Release: 73 +Release: 76 Summary: The GNU libc libraries License: %{all_license} URL: http://www.gnu.org/software/glibc/ @@ -360,6 +360,13 @@ Patch270: x86-64-Add-GLIBC_ABI_GNU2_TLS-version-BZ-33129.patch Patch271: i386-Also-add-GLIBC_ABI_GNU2_TLS-version-BZ-33129.patch Patch272: i386-Add-GLIBC_ABI_GNU_TLS-version-BZ-33221.patch Patch273: backport-Free-dynarray-buffer-after-parsing-nsswitch.conf.patch +Patch274: LoongArch-Update-ulps.patch +Patch275: Add-HWCAP_LOONGARCH_LSPW-from-Linux-6.12-to-bits-hwc.patch +Patch276: loongarch-Provide-stpcpy-in-stpcpy-aligned.S-for-rtl.patch +Patch277: loongarch-Drop-__GI_XXX-for-strcpy-stpcpy-IFUNC-impl.patch +Patch278: x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch +Patch279: x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch +Patch280: x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch #openEuler patch list Patch9000: turn-default-value-of-x86_rep_stosb_threshold_form_2K_to_1M.patch @@ -408,8 +415,8 @@ Patch9039: revert-aarch64-Use-memcpy_simd-as-the-default-memcpy.patch Patch9040: backport-Fix-UB-on__dl_map_object_from_fd.patch Patch9041: backport-Fix-handling-of-symbol-versions-which-hash-to-zero.patch Patch9042: AArch64-modify_the_SVE_memcpy_implementation_for_32-byte_aligned_access.patch - Patch9043: 0024-Sw64-Change-libdir-from-lib-to-lib64.patch +Patch9044: backport-x86-Disable-AVX-Fast-Unaligned-Load-on-Hygon-1-2-3.patch Provides: ldconfig rtld(GNU_HASH) bundled(gnulib) @@ -1596,6 +1603,17 @@ fi %endif %changelog +* Mon Nov 03 2025 Qingqing Li - 2.38-76 +- x86: Skip XSAVE state size reset if ISA level requires XSAVE +- x86-64: Simplify minimum ISA check ifdef conditional with if +- x86-64: Don't use SSE resolvers for ISA level 3 or above + +* Mon Oct 27 2025 litenglong - 2.38-75 +- x86: Disable AVX Fast Unaligned Load on Hygon 1/2/3 + +* Wed Oct 22 2025 Peng Fan - 2.38-74 +- LoongArch: Sync from glibc upstream + * Mon Oct 20 2025 swcompiler - 2.38-73 - Sw64:Change libdir from lib to lib64 diff --git a/loongarch-Drop-__GI_XXX-for-strcpy-stpcpy-IFUNC-impl.patch b/loongarch-Drop-__GI_XXX-for-strcpy-stpcpy-IFUNC-impl.patch new file mode 100644 index 0000000000000000000000000000000000000000..63b8e1055ef8312921f6ef2b1376ac94928f5adb --- /dev/null +++ b/loongarch-Drop-__GI_XXX-for-strcpy-stpcpy-IFUNC-impl.patch @@ -0,0 +1,61 @@ +From fb7ee7cf7743ec8358678516e3e73471491a995f Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Sat, 4 Jan 2025 05:53:19 +0800 +Subject: [PATCH 4/4] loongarch: Drop __GI_XXX for strcpy/stpcpy IFUNC + implementations + +There is no need for __GI_XXX symbols, like __GI___strcpy_aligned since +__strcpy_aligned is used directly. + +Signed-off-by: H.J. Lu +Reviewed-by: Sam James +--- + sysdeps/loongarch/lp64/multiarch/strcpy-aligned.S | 2 -- + sysdeps/loongarch/lp64/multiarch/strcpy-lasx.S | 1 - + sysdeps/loongarch/lp64/multiarch/strcpy-lsx.S | 1 - + sysdeps/loongarch/lp64/multiarch/strcpy-unaligned.S | 1 - + 4 files changed, 5 deletions(-) + +diff --git a/sysdeps/loongarch/lp64/multiarch/strcpy-aligned.S b/sysdeps/loongarch/lp64/multiarch/strcpy-aligned.S +index 4ed539fd..1913fa63 100644 +--- a/sysdeps/loongarch/lp64/multiarch/strcpy-aligned.S ++++ b/sysdeps/loongarch/lp64/multiarch/strcpy-aligned.S +@@ -198,5 +198,3 @@ L(un_out): + #endif + jr ra + END(STRCPY) +- +-libc_hidden_builtin_def (STRCPY) +diff --git a/sysdeps/loongarch/lp64/multiarch/strcpy-lasx.S b/sysdeps/loongarch/lp64/multiarch/strcpy-lasx.S +index c2825612..3f20d359 100644 +--- a/sysdeps/loongarch/lp64/multiarch/strcpy-lasx.S ++++ b/sysdeps/loongarch/lp64/multiarch/strcpy-lasx.S +@@ -211,5 +211,4 @@ L(zero_byte): + jr ra + END(STRCPY) + +-libc_hidden_builtin_def (STRCPY) + #endif +diff --git a/sysdeps/loongarch/lp64/multiarch/strcpy-lsx.S b/sysdeps/loongarch/lp64/multiarch/strcpy-lsx.S +index fc2498f7..b3e7ec89 100644 +--- a/sysdeps/loongarch/lp64/multiarch/strcpy-lsx.S ++++ b/sysdeps/loongarch/lp64/multiarch/strcpy-lsx.S +@@ -208,5 +208,4 @@ L(INDEX): + .dword 0x0706050403020100 + .dword 0x0f0e0d0c0b0a0908 + +-libc_hidden_builtin_def (STRCPY) + #endif +diff --git a/sysdeps/loongarch/lp64/multiarch/strcpy-unaligned.S b/sysdeps/loongarch/lp64/multiarch/strcpy-unaligned.S +index 9e31883b..fee2a7c4 100644 +--- a/sysdeps/loongarch/lp64/multiarch/strcpy-unaligned.S ++++ b/sysdeps/loongarch/lp64/multiarch/strcpy-unaligned.S +@@ -134,5 +134,4 @@ L(page_cross): + b L(end) + END(STRCPY) + +-libc_hidden_builtin_def (STRCPY) + #endif +-- +2.47.3 + diff --git a/loongarch-Provide-stpcpy-in-stpcpy-aligned.S-for-rtl.patch b/loongarch-Provide-stpcpy-in-stpcpy-aligned.S-for-rtl.patch new file mode 100644 index 0000000000000000000000000000000000000000..d837523e6aabbb7af60bf20bd5ce6505bea6780b --- /dev/null +++ b/loongarch-Provide-stpcpy-in-stpcpy-aligned.S-for-rtl.patch @@ -0,0 +1,29 @@ +From d505aa00528b702c9fb451ada22055598d8c76c8 Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Sat, 4 Jan 2025 05:43:21 +0800 +Subject: [PATCH 3/4] loongarch: Provide stpcpy in stpcpy-aligned.S for rtld + [BZ #32512] + +When stpcpy-aligned.S is used in rtld, provide stpcpy as a weak alias of +__stpcpy. This fixes BZ #32512. + +Signed-off-by: H.J. Lu +--- + sysdeps/loongarch/lp64/multiarch/stpcpy-aligned.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sysdeps/loongarch/lp64/multiarch/stpcpy-aligned.S b/sysdeps/loongarch/lp64/multiarch/stpcpy-aligned.S +index 1f763db6..99f2c270 100644 +--- a/sysdeps/loongarch/lp64/multiarch/stpcpy-aligned.S ++++ b/sysdeps/loongarch/lp64/multiarch/stpcpy-aligned.S +@@ -20,6 +20,7 @@ + # define STPCPY __stpcpy_aligned + #else + # define STPCPY __stpcpy ++weak_alias (__stpcpy, stpcpy) + #endif + + #define USE_AS_STPCPY +-- +2.47.3 + diff --git a/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch b/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch new file mode 100644 index 0000000000000000000000000000000000000000..e6090ccc0621c66abd6b780e2546d2f7876cef70 --- /dev/null +++ b/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch @@ -0,0 +1,114 @@ +From 7dfafa866d803aaac5645a5c4ed917d1948c771b Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Wed, 28 Feb 2024 09:51:14 -0800 +Subject: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above + +When glibc is built with ISA level 3 or above enabled, SSE resolvers +aren't available and glibc fails to build: + +ld: .../elf/librtld.os: in function `init_cpu_features': +.../elf/../sysdeps/x86/cpu-features.c:1200:(.text+0x1445f): undefined reference to `_dl_runtime_resolve_fxsave' +ld: .../elf/librtld.os: relocation R_X86_64_PC32 against undefined hidden symbol `_dl_runtime_resolve_fxsave' can not be used when making a shared object +/usr/local/bin/ld: final link failed: bad value + +For ISA level 3 or above, don't use _dl_runtime_resolve_fxsave nor +_dl_tlsdesc_dynamic_fxsave. + +This fixes BZ #31429. +Reviewed-by: Noah Goldstein + +(cherry picked from commit befe2d3c4dec8be2cdd01a47132e47bdb7020922) +--- + sysdeps/x86/cpu-features.c | 17 +++++++++++------ + sysdeps/x86_64/dl-tlsdesc.S | 15 +++++++++------ + 2 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 975b75c68b..051d8c2536 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -18,6 +18,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -1116,7 +1117,9 @@ no_cpuid: + TUNABLE_CALLBACK (set_x86_shstk)); + #endif + ++#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + if (GLRO(dl_x86_cpu_features).xsave_state_size != 0) ++#endif + { + if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC)) + { +@@ -1137,22 +1140,24 @@ no_cpuid: + #endif + } + } ++#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + else + { +-#ifdef __x86_64__ ++# ifdef __x86_64__ + GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave; +-# ifdef SHARED ++# ifdef SHARED + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; +-# endif +-#else +-# ifdef SHARED ++# endif ++# else ++# ifdef SHARED + if (CPU_FEATURE_USABLE_P (cpu_features, FXSR)) + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; + else + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave; ++# endif + # endif +-#endif + } ++#endif + + #ifndef SHARED + /* NB: In libc.a, call init_cacheinfo. */ +diff --git a/sysdeps/x86_64/dl-tlsdesc.S b/sysdeps/x86_64/dl-tlsdesc.S +index 1b80dd8a8c..a8889cdfd0 100644 +--- a/sysdeps/x86_64/dl-tlsdesc.S ++++ b/sysdeps/x86_64/dl-tlsdesc.S +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include "tlsdesc.h" + + /* Area on stack to save and restore registers used for parameter +@@ -78,12 +79,14 @@ _dl_tlsdesc_undefweak: + .size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak + + #ifdef SHARED +-# define USE_FXSAVE +-# define STATE_SAVE_ALIGNMENT 16 +-# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave +-# include "dl-tlsdesc-dynamic.h" +-# undef _dl_tlsdesc_dynamic +-# undef USE_FXSAVE ++# if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL ++# define USE_FXSAVE ++# define STATE_SAVE_ALIGNMENT 16 ++# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave ++# include "dl-tlsdesc-dynamic.h" ++# undef _dl_tlsdesc_dynamic ++# undef USE_FXSAVE ++# endif + + # define USE_XSAVE + # define STATE_SAVE_ALIGNMENT 64 +-- +2.27.0 + diff --git a/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch b/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch new file mode 100644 index 0000000000000000000000000000000000000000..c4f0566ea906b50ab25a187cdc2785868f7e2f05 --- /dev/null +++ b/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch @@ -0,0 +1,67 @@ +From 554716698b6f497f098b60f21a3da0d1207b376a Mon Sep 17 00:00:00 2001 +From: Sunil K Pandey +Date: Thu, 29 Feb 2024 17:57:02 -0800 +Subject: [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with + if + +Replace minimum ISA check ifdef conditional with if. Since +MINIMUM_X86_ISA_LEVEL and AVX_X86_ISA_LEVEL are compile time constants, +compiler will perform constant folding optimization, getting same +results. + +Reviewed-by: H.J. Lu +(cherry picked from commit b6e3898194bbae78910bbe9cd086937014961e45) +--- + sysdeps/x86/cpu-features.c | 19 ++++++++----------- + 1 file changed, 8 insertions(+), 11 deletions(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 051d8c2536..4570d3d075 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -1117,9 +1117,8 @@ no_cpuid: + TUNABLE_CALLBACK (set_x86_shstk)); + #endif + +-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL +- if (GLRO(dl_x86_cpu_features).xsave_state_size != 0) +-#endif ++ if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL ++ || (GLRO(dl_x86_cpu_features).xsave_state_size != 0)) + { + if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC)) + { +@@ -1140,24 +1139,22 @@ no_cpuid: + #endif + } + } +-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + else + { +-# ifdef __x86_64__ ++#ifdef __x86_64__ + GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave; +-# ifdef SHARED ++# ifdef SHARED + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; +-# endif +-# else +-# ifdef SHARED ++# endif ++#else ++# ifdef SHARED + if (CPU_FEATURE_USABLE_P (cpu_features, FXSR)) + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; + else + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave; +-# endif + # endif +- } + #endif ++ } + + #ifndef SHARED + /* NB: In libc.a, call init_cacheinfo. */ +-- +2.27.0 + diff --git a/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch b/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch new file mode 100644 index 0000000000000000000000000000000000000000..b0bfd04fcf7313103912348b0de552c9434b3ab9 --- /dev/null +++ b/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch @@ -0,0 +1,53 @@ +From 815233f54b947169b5806dbddcde5f88b3be59e4 Mon Sep 17 00:00:00 2001 +From: Florian Weimer +Date: Fri, 28 Mar 2025 09:26:06 +0100 +Subject: [PATCH] x86: Skip XSAVE state size reset if ISA level requires + XSAVE + +If we have to use XSAVE or XSAVEC trampolines, do not adjust the size +information they need. Technically, it is an operator error to try to +run with -XSAVE,-XSAVEC on such builds, but this change here disables +some unnecessary code with higher ISA levels and simplifies testing. + +Related to commit befe2d3c4dec8be2cdd01a47132e47bdb7020922 +("x86-64: Don't use SSE resolvers for ISA level 3 or above"). + +Reviewed-by: H.J. Lu +(cherry picked from commit 59585ddaa2d44f22af04bb4b8bd4ad1e302c4c02) +--- + sysdeps/x86/cpu-features.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 4570d3d075..4048c88f7f 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) + attribute_hidden; +@@ -1010,6 +1011,9 @@ no_cpuid: + TUNABLE_CALLBACK (set_prefer_map_32bit_exec)); + #endif + ++ /* Do not add the logic to disable XSAVE/XSAVEC if this glibc build ++ requires AVX and therefore XSAVE or XSAVEC support. */ ++#ifndef GCCMACRO__AVX__ + bool disable_xsave_features = false; + + if (!CPU_FEATURE_USABLE_P (cpu_features, OSXSAVE)) +@@ -1063,6 +1067,7 @@ no_cpuid: + + CPU_FEATURE_UNSET (cpu_features, FMA4); + } ++#endif + + #ifdef __x86_64__ + GLRO(dl_hwcap) = HWCAP_X86_64; +-- +2.27.0 +