diff --git a/glibc.spec b/glibc.spec index 1a3d265c4e2a439850c00c9b1cc19094f151a444..a331490a70cce7a42a3be273d5b5a4a678a36f9a 100644 --- a/glibc.spec +++ b/glibc.spec @@ -67,7 +67,7 @@ ############################################################################## Name: glibc Version: 2.38 -Release: 73 +Release: 74 Summary: The GNU libc libraries License: %{all_license} URL: http://www.gnu.org/software/glibc/ @@ -363,6 +363,9 @@ Patch273: LoongArch-Update-ulps.patch Patch274: Add-HWCAP_LOONGARCH_LSPW-from-Linux-6.12-to-bits-hwc.patch Patch275: loongarch-Provide-stpcpy-in-stpcpy-aligned.S-for-rtl.patch Patch276: loongarch-Drop-__GI_XXX-for-strcpy-stpcpy-IFUNC-impl.patch +Patch277: x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch +Patch278: x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch +Patch279: x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch #openEuler patch list Patch9000: turn-default-value-of-x86_rep_stosb_threshold_form_2K_to_1M.patch @@ -1598,6 +1601,11 @@ fi %endif %changelog +* Mon Nov 03 2025 Qingqing Li - 2.38-74 +- x86: Skip XSAVE state size reset if ISA level requires XSAVE +- x86-64: Simplify minimum ISA check ifdef conditional with if +- x86-64: Don't use SSE resolvers for ISA level 3 or above + * Mon Oct 27 2025 litenglong - 2.38-73 - x86: Disable AVX Fast Unaligned Load on Hygon 1/2/3 diff --git a/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch b/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch new file mode 100644 index 0000000000000000000000000000000000000000..e6090ccc0621c66abd6b780e2546d2f7876cef70 --- /dev/null +++ b/x86-64-Don-t-use-SSE-resolvers-for-ISA-level-3-or-ab.patch @@ -0,0 +1,114 @@ +From 7dfafa866d803aaac5645a5c4ed917d1948c771b Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Wed, 28 Feb 2024 09:51:14 -0800 +Subject: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above + +When glibc is built with ISA level 3 or above enabled, SSE resolvers +aren't available and glibc fails to build: + +ld: .../elf/librtld.os: in function `init_cpu_features': +.../elf/../sysdeps/x86/cpu-features.c:1200:(.text+0x1445f): undefined reference to `_dl_runtime_resolve_fxsave' +ld: .../elf/librtld.os: relocation R_X86_64_PC32 against undefined hidden symbol `_dl_runtime_resolve_fxsave' can not be used when making a shared object +/usr/local/bin/ld: final link failed: bad value + +For ISA level 3 or above, don't use _dl_runtime_resolve_fxsave nor +_dl_tlsdesc_dynamic_fxsave. + +This fixes BZ #31429. +Reviewed-by: Noah Goldstein + +(cherry picked from commit befe2d3c4dec8be2cdd01a47132e47bdb7020922) +--- + sysdeps/x86/cpu-features.c | 17 +++++++++++------ + sysdeps/x86_64/dl-tlsdesc.S | 15 +++++++++------ + 2 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 975b75c68b..051d8c2536 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -18,6 +18,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -1116,7 +1117,9 @@ no_cpuid: + TUNABLE_CALLBACK (set_x86_shstk)); + #endif + ++#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + if (GLRO(dl_x86_cpu_features).xsave_state_size != 0) ++#endif + { + if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC)) + { +@@ -1137,22 +1140,24 @@ no_cpuid: + #endif + } + } ++#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + else + { +-#ifdef __x86_64__ ++# ifdef __x86_64__ + GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave; +-# ifdef SHARED ++# ifdef SHARED + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; +-# endif +-#else +-# ifdef SHARED ++# endif ++# else ++# ifdef SHARED + if (CPU_FEATURE_USABLE_P (cpu_features, FXSR)) + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; + else + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave; ++# endif + # endif +-#endif + } ++#endif + + #ifndef SHARED + /* NB: In libc.a, call init_cacheinfo. */ +diff --git a/sysdeps/x86_64/dl-tlsdesc.S b/sysdeps/x86_64/dl-tlsdesc.S +index 1b80dd8a8c..a8889cdfd0 100644 +--- a/sysdeps/x86_64/dl-tlsdesc.S ++++ b/sysdeps/x86_64/dl-tlsdesc.S +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include "tlsdesc.h" + + /* Area on stack to save and restore registers used for parameter +@@ -78,12 +79,14 @@ _dl_tlsdesc_undefweak: + .size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak + + #ifdef SHARED +-# define USE_FXSAVE +-# define STATE_SAVE_ALIGNMENT 16 +-# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave +-# include "dl-tlsdesc-dynamic.h" +-# undef _dl_tlsdesc_dynamic +-# undef USE_FXSAVE ++# if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL ++# define USE_FXSAVE ++# define STATE_SAVE_ALIGNMENT 16 ++# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave ++# include "dl-tlsdesc-dynamic.h" ++# undef _dl_tlsdesc_dynamic ++# undef USE_FXSAVE ++# endif + + # define USE_XSAVE + # define STATE_SAVE_ALIGNMENT 64 +-- +2.27.0 + diff --git a/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch b/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch new file mode 100644 index 0000000000000000000000000000000000000000..c4f0566ea906b50ab25a187cdc2785868f7e2f05 --- /dev/null +++ b/x86-64-Simplify-minimum-ISA-check-ifdef-conditional-.patch @@ -0,0 +1,67 @@ +From 554716698b6f497f098b60f21a3da0d1207b376a Mon Sep 17 00:00:00 2001 +From: Sunil K Pandey +Date: Thu, 29 Feb 2024 17:57:02 -0800 +Subject: [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with + if + +Replace minimum ISA check ifdef conditional with if. Since +MINIMUM_X86_ISA_LEVEL and AVX_X86_ISA_LEVEL are compile time constants, +compiler will perform constant folding optimization, getting same +results. + +Reviewed-by: H.J. Lu +(cherry picked from commit b6e3898194bbae78910bbe9cd086937014961e45) +--- + sysdeps/x86/cpu-features.c | 19 ++++++++----------- + 1 file changed, 8 insertions(+), 11 deletions(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 051d8c2536..4570d3d075 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -1117,9 +1117,8 @@ no_cpuid: + TUNABLE_CALLBACK (set_x86_shstk)); + #endif + +-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL +- if (GLRO(dl_x86_cpu_features).xsave_state_size != 0) +-#endif ++ if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL ++ || (GLRO(dl_x86_cpu_features).xsave_state_size != 0)) + { + if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC)) + { +@@ -1140,24 +1139,22 @@ no_cpuid: + #endif + } + } +-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL + else + { +-# ifdef __x86_64__ ++#ifdef __x86_64__ + GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave; +-# ifdef SHARED ++# ifdef SHARED + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; +-# endif +-# else +-# ifdef SHARED ++# endif ++#else ++# ifdef SHARED + if (CPU_FEATURE_USABLE_P (cpu_features, FXSR)) + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave; + else + GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave; +-# endif + # endif +- } + #endif ++ } + + #ifndef SHARED + /* NB: In libc.a, call init_cacheinfo. */ +-- +2.27.0 + diff --git a/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch b/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch new file mode 100644 index 0000000000000000000000000000000000000000..b0bfd04fcf7313103912348b0de552c9434b3ab9 --- /dev/null +++ b/x86-Skip-XSAVE-state-size-reset-if-ISA-level-require.patch @@ -0,0 +1,53 @@ +From 815233f54b947169b5806dbddcde5f88b3be59e4 Mon Sep 17 00:00:00 2001 +From: Florian Weimer +Date: Fri, 28 Mar 2025 09:26:06 +0100 +Subject: [PATCH] x86: Skip XSAVE state size reset if ISA level requires + XSAVE + +If we have to use XSAVE or XSAVEC trampolines, do not adjust the size +information they need. Technically, it is an operator error to try to +run with -XSAVE,-XSAVEC on such builds, but this change here disables +some unnecessary code with higher ISA levels and simplifies testing. + +Related to commit befe2d3c4dec8be2cdd01a47132e47bdb7020922 +("x86-64: Don't use SSE resolvers for ISA level 3 or above"). + +Reviewed-by: H.J. Lu +(cherry picked from commit 59585ddaa2d44f22af04bb4b8bd4ad1e302c4c02) +--- + sysdeps/x86/cpu-features.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index 4570d3d075..4048c88f7f 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *) + attribute_hidden; +@@ -1010,6 +1011,9 @@ no_cpuid: + TUNABLE_CALLBACK (set_prefer_map_32bit_exec)); + #endif + ++ /* Do not add the logic to disable XSAVE/XSAVEC if this glibc build ++ requires AVX and therefore XSAVE or XSAVEC support. */ ++#ifndef GCCMACRO__AVX__ + bool disable_xsave_features = false; + + if (!CPU_FEATURE_USABLE_P (cpu_features, OSXSAVE)) +@@ -1063,6 +1067,7 @@ no_cpuid: + + CPU_FEATURE_UNSET (cpu_features, FMA4); + } ++#endif + + #ifdef __x86_64__ + GLRO(dl_hwcap) = HWCAP_X86_64; +-- +2.27.0 +