# chisel
**Repository Path**: qturing/chisel
## Basic Information
- **Project Name**: chisel
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Apache-2.0
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No
## Statistics
- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-09-22
- **Last Updated**: 2025-09-24
## Categories & Tags
**Categories**: Uncategorized
**Tags**: None
## README
The **Constructing Hardware in a Scala Embedded Language** ([**Chisel**](https://www.chisel-lang.org)) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates **advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs**.
[Chisel](https://www.chisel-lang.org)，基于Scala的嵌入式硬件构建语言,是一个开源的硬件描述语言，用于描述数字电路和电路的寄存器传输级，为ASIC和FPGA数字逻辑设计的高级电路生成和设计复用提供了一种基于Scala的嵌入式硬件构建语言。
Chisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
Chisel添加硬件构建原语到[Scala程序语言](https://www.scala-lang.org)，为设计者提供使用现代编程语言的能力，编写复杂、参数化的电路生成器，并产生可综合的Verilog。
This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/#chisel3.util.package), raising the level of abstraction in design while retaining fine-grained control.
这种生成器方法学，使得创建可复用组件和库成为可能，如[Chisel标准库](https://www.chisel-lang.org/api/latest/#chisel3.util.package)的FIFO队列和仲裁器，在设计中提高抽象程度，并保留细粒度的控制。
For more information on the benefits of Chisel see: ["What benefits does Chisel offer over classic Hardware Description Languages?"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages)
有关Chisel的益处，请参阅：["Chisel有什么好处呢？"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages)
Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/chipsalliance/firrtl-spec),
a hardware compiler framework implemented by [LLVM CIRCT](https://github.com/llvm/circt).
Chisel由[FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/chipsalliance/firrtl-spec)赋能，FIRRTL是由[LLVM CIRCT](https://github.com/llvm/circt)实现的硬件编译框架。
Chisel is [permissively licensed](LICENSE) (Apache 2.0) under the guidance of [CHIPS Alliance](https://www.chipsalliance.org).
Chisel是有限授权的开源硬件描述语言，由[CHIPS Alliance](https://www.chipsalliance.org)指导。
- [What does Chisel code look like? // chisel代码的样子](#what-does-chisel-code-look-like--chisel代码的样子)
- [LED blink // 闪烁的LED灯](#led-blink--闪烁的led灯)
- [FIR Filter // FIR滤波器](#fir-filter--fir滤波器)
- [Getting Started // 开始](#getting-started--开始)
- [Bootcamp Interactive Tutorial // Bootcamp交互教程](#bootcamp-interactive-tutorial--bootcamp交互教程)
- [A Textbook on Chisel // Chisel 手册](#a-textbook-on-chisel--chisel-手册)
- [Build Your Own Chisel Projects](#build-your-own-chisel-projects)
- [Guide For New Contributors // 新贡献者指南](#guide-for-new-contributors--新贡献者指南)
- [Design Verification // 设计验证](#design-verification--设计验证)
- [Documentation // 文档](#documentation--文档)
- [Useful Resources // 有用的资源](#useful-resources--有用的资源)
- [Chisel Dev Meeting // chisel 开发会议](#chisel-dev-meeting--chisel-开发会议)
- [Data Types Overview // 数据类型概述](#data-types-overview--数据类型概述)
- [Contributor Documentation // 贡献者文档](#contributor-documentation--贡献者文档)
- [Useful Resources for Contributors // 贡献者资源](#useful-resources-for-contributors--贡献者资源)
- [Compiling and Testing Chisel // 编译和测试 Chisel](#compiling-and-testing-chisel--编译和测试-chisel)
- [Running Projects Against Local Chisel // 运行项目对本地 Chisel](#running-projects-against-local-chisel--运行项目对本地-chisel)
- [Chisel Architecture Overview // Chisel 架构概述](#chisel-architecture-overview--chisel-架构概述)
- [Chisel Sub-Projects // Chisel 子项目](#chisel-sub-projects--chisel-子项目)
- [Which version should I use? // 哪个版本应该使用？](#which-version-should-i-use--哪个版本应该使用)
- [Roadmap // 路线图](#roadmap--路线图)
---
[](https://gitter.im/freechipsproject/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
[](https://javadoc.io/doc/org.chipsalliance/chisel_2.13/latest)
[](https://github.com/chipsalliance/chisel/releases/latest)
[](https://index.scala-lang.org/chipsalliance/chisel/chisel)
[](https://index.scala-lang.org/chipsalliance/chisel/chisel3)
[](https://s01.oss.sonatype.org/content/repositories/snapshots/org/chipsalliance/chisel_2.13)
## What does Chisel code look like? // chisel代码的样子
### LED blink // 闪烁的LED灯
```scala
import chisel3._
import chisel3.util.Counter
import circt.stage.ChiselStage
class Blinky(freq: Int, startOn: Boolean = false) extends Module {
val io = IO(new Bundle {
val led0 = Output(Bool())
})
// Blink LED every second using Chisel built-in util.Counter
val led = RegInit(startOn.B)
val (_, counterWrap) = Counter(true.B, freq / 2)
when(counterWrap) {
led := ~led
}
io.led0 := led
}
object Main extends App {
// These lines generate the Verilog output
println(
ChiselStage.emitSystemVerilog(
new Blinky(1000),
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```
Should output the following Verilog:
Click to expand!
module Blinky(
input clock,
reset,
output io_led0
);
reg led;
reg [8:0] counterWrap_c_value;
always @(posedge clock) begin
if (reset) begin
led <= 1'h0;
counterWrap_c_value <= 9'h0;
end
else begin
automatic logic counterWrap = counterWrap_c_value == 9'h1F3;
led <= counterWrap ^ led;
if (counterWrap)
counterWrap_c_value <= 9'h0;
else
counterWrap_c_value <= counterWrap_c_value + 9'h1;
end
end
assign io_led0 = led;
endmodule
### FIR Filter // FIR滤波器
Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:
FIR滤波器实现卷积操作的块图：
While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such:
同时，Chisel提供了相似的基本原语，并且可以作为可 synthesizable Verilog使用：
```scala
// 3-point moving sum implemented in the style of a FIR filter
class MovingSum3(bitWidth: Int) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(bitWidth.W))
val out = Output(UInt(bitWidth.W))
})
val z1 = RegNext(io.in)
val z2 = RegNext(z1)
io.out := (io.in * 1.U) + (z1 * 1.U) + (z2 * 1.U)
}
```
the power of Chisel comes from the ability to create generators, such as an FIR filter that is defined by the list of coefficients:
Chisel的能力是生成器，比如，通过系数列表定义的 FIR 滤波器：
```scala
// Generalized FIR filter parameterized by the convolution coefficients
class FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(bitWidth.W))
val out = Output(UInt(bitWidth.W))
})
// Create the serial-in, parallel-out shift register
val zs = Reg(Vec(coeffs.length, UInt(bitWidth.W)))
zs(0) := io.in
for (i <- 1 until coeffs.length) {
zs(i) := zs(i-1)
}
// Do the multiplies
val products = VecInit.tabulate(coeffs.length)(i => zs(i) * coeffs(i))
// Sum up the products
io.out := products.reduce(_ + _)
}
```
and use and re-use them across designs:
在设计中使用和重用 FIR 滤波器：
```scala
val movingSum3Filter = Module(new FirFilter(8, Seq(1.U, 1.U, 1.U))) // same 3-point moving sum filter as before
val delayFilter = Module(new FirFilter(8, Seq(0.U, 1.U))) // 1-cycle delay as a FIR filter
val triangleFilter = Module(new FirFilter(8, Seq(1.U, 2.U, 3.U, 2.U, 1.U))) // 5-point FIR filter with a triangle impulse response
```
The above can be converted to Verilog using `ChiselStage`:
上面的内容可以使用 `ChiselStage` 转换为 Verilog：
```scala
import chisel3.stage.ChiselGeneratorAnnotation
import circt.stage.{ChiselStage, FirtoolOption}
(new ChiselStage).execute(
Array("--target", "systemverilog"),
Seq(ChiselGeneratorAnnotation(() => new FirFilter(8, Seq(1.U, 1.U, 1.U))),
FirtoolOption("--disable-all-randomization"))
)
```
Alternatively, you may generate some Verilog directly for inspection:
或者，可以生成某些 Verilog 用于检查：
```scala
val verilogString = chisel3.getVerilogString(new FirFilter(8, Seq(0.U, 1.U)))
println(verilogString)
```
## Getting Started // 开始
### Bootcamp Interactive Tutorial // Bootcamp交互教程
The [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) is the recommended way to get started with and learn Chisel.
[线上的 Chisel Bootcamp](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) 是推荐的方式来开始使用和学习 Chisel。
**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala.
不需要安装，也不需要任何 Scala 的先验知识。
The [**classic Chisel tutorial**](https://github.com/ucb-bar/chisel-tutorial) contains small exercises and runs on your computer.
[**经典 Chisel 教程**](https://github.com/ucb-bar/chisel-tutorial) 包含一些小练习，并在你的计算机上运行。
### A Textbook on Chisel // Chisel 手册
If you like a textbook to learn Chisel and also a bit of digital design in general, you may be interested in reading [**Digital Design with Chisel**](http://www.imm.dtu.dk/~masca/chisel-book.html). It is available in English, Chinese, Japanese, and Vietnamese.
如果你喜欢一个手册来学习 Chisel，并且也想学习数字设计，你可能会感兴趣的阅读 [**Digital Design with Chisel**](http://www.imm.dtu.dk/~masca/chisel-book.html)。 该手册可用英语、中文、日语和越南语。
### Build Your Own Chisel Projects
Please see [the Installation page](https://www.chisel-lang.org/docs/installation) of the Chisel website for information about how to use Chisel locally.
访问 Chisel 网站的 [安装页面](https://www.chisel-lang.org/docs/installation)，了解如何使用 Chisel 本地。
When you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/chipsalliance/chisel-template) repository**, which provides a pre-configured project, example design, and testbench.
当你准备使用 Chisel 构建自己的电路时，**我们建议从 [Chisel 模板](https://github.com/chipsalliance/chisel-template) 仓库开始**，该仓库提供了预配置的项目、示例设计和测试样例。
Follow the [chisel-template README](https://github.com/chipsalliance/chisel-template) to get started.
访问 Chisel 模板的 [README](https://github.com/chipsalliance/chisel-template)，开始使用。
If you insist on setting up your own project from scratch, your project needs to depend on both the chisel-plugin (Scalac plugin) and the chisel library.
如果坚持从零开始设置项目，你的项目需要依赖 chisel-plugin（Scalac 插件）和 chisel 库。
For example, in SBT this could be expressed as:
例如，在 SBT 中，这可以表达为：
```scala
// build.sbt
scalaVersion := "2.13.12"
val chiselVersion = "6.0.0"
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
```
For Chisel prior to v5.0.0, Chisel was published using a different artifact name:
对于 Chisel 之前的 v5.0.0，Chisel 被发布使用不同的工件名称：
```scala
// build.sbt
scalaVersion := "2.13.10"
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.6.0"
// We also recommend using chiseltest for writing unit tests
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0" % "test"
```
### Guide For New Contributors // 新贡献者指南
If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](CONTRIBUTING.md).
如果你正在尝试为这个项目做出贡献，请阅读 [CONTRIBUTING.md](CONTRIBUTING.md)。
### Design Verification // 设计验证
These simulation-based verification tools are available for Chisel:
这些模拟驱动的验证工具可用于 Chisel：
* [**svsim**](svsim) is the lightweight testing library for Chisel, included in this repository.
**svsim** 是 Chisel 的轻量级测试库， included in this repository.
* [**chiseltest (Chisel 6.0 and before)**](https://github.com/ucb-bar/chiseltest) is the batteries-included testing and formal verification library for Chisel-based RTL designs and a replacement for the former PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with `fork` and `join` with internal and Verilator integration for simulations.
**chiseltest (Chisel 6.0 和之前)** 是 Chisel 基于 RTL 设计的电池式测试和形式验证库，替代了以前的 PeekPokeTester，提供了相同的基本构造，但具有简化的界面和内部并发支持，使用 `fork` 和 `join`，以及内置和 Verilator 的集成进行仿真。
## Documentation // 文档
### Useful Resources // 有用的资源
* [**Cheat Sheet**](https://github.com/freechipsproject/chisel-cheatsheet/releases/latest/download/chisel_cheatsheet.pdf), a 2-page reference of the base Chisel syntax and libraries
一个基础 Chisel 语法和库的 2 页参考
* [**ScalaDoc (latest)**](https://www.chisel-lang.org/api/latest/index.html), a listing, description, and examples of the functionality exposed by Chisel, [older versions](https://www.chisel-lang.org/api/) are also available
一个列表，描述和示例，Chisel 公开的功能，[旧版本](https://www.chisel-lang.org/api/)也可用
* [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel
帮助助您提问或讨论任何 Chisel 的问题
* [**Website**](https://www.chisel-lang.org) ([source](website))
chisel 网站
* [**Scastie (v6.0.0)**](https://scastie.scala-lang.org/CsDO7Q3TQHmBWJfKEB85Tw) - cannot generate Verilog (firtool does not work in Scastie)
不能生成 Verilog（ firtool 不在 Scastie 中工作）
* [**Scastie (v3.6.0)**](https://scastie.scala-lang.org/1XICrlaZQs6ZvxpuKdFdDw) - generates Verilog with legacy Scala FIRRTL Compiler
生成 Verilog （使用旧版 Scala FIRRTL 编译器）
* [**asic-world**](http://www.asic-world.com/verilog/veritut.html) If you aren't familiar with verilog, this is a good tutorial.
如果您对 verilog 不熟悉，这是一个好教程。
If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/docs/appendix/chisel3-vs-chisel2.html).
如果正在从 Chisel2 迁移，请查看 [迁移指南](https://www.chisel-lang.org/chisel3/docs/appendix/chisel3-vs-chisel2.html)。
### Chisel Dev Meeting // chisel 开发会议
Chisel/FIRRTL development meetings happen every Monday from 9:00-10:00 am PT.
Chisel/FIRRTL 开发会议每星期从 9:00-10:00 am PT 开始。
Call-in info and meeting notes are available [here](https://docs.google.com/document/d/1BLP2DYt59DqI-FgFCcjw8Ddl4K-WU0nHmQu0sZ_wAGo/).
会议记录和会议信息都在这里。
### Data Types Overview // 数据类型概述
These are the base data types for defining circuit components:
基础数据类型用于定义电路组件：
## Contributor Documentation // 贡献者文档
This section describes how to get started contributing to Chisel itself, including how to test your version locally against other projects that pull in Chisel using [sbt's managed dependencies](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html).
这一节描述如何开始贡献到 Chisel 本身，包括如何使用 [sbt 的管理依赖项](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html) 来测试您的本地版本。
### Useful Resources for Contributors // 贡献者资源
The [Useful Resources](#useful-resources) for users are also helpful for contributors.
贡献者资源中的 [Useful Resources](#useful-resources) 也对贡献者有用。
* [**Chisel Breakdown Slides**](https://docs.google.com/presentation/d/1gMtABxBEDFbCFXN_-dPyvycNAyFROZKwk-HMcnxfTnU/edit?usp=sharing), an introductory talk about Chisel's internals
Chisel 的内部工作原理
### Compiling and Testing Chisel // 编译和测试 Chisel
You must first install required dependencies to build Chisel locally, please see [the installation instructions](https://www.chisel-lang.org/docs/installation).
你必须安装一些依赖项才能编译 Chisel 本身，请查看 [安装说明](https://www.chisel-lang.org/docs/installation)。
Clone and build the Chisel library:
克隆和构建 Chisel 库：
```bash
git clone https://github.com/chipsalliance/chisel.git
cd chisel
./mill chisel[].compile
```
In order to run the following unit tests, you will need several tools on your `PATH`, namely
为了运行以下单元测试，你需要在 `PATH` 上安装一些工具：
[verilator](https://www.veripool.org/verilator/),
[yosys](https://yosyshq.net/yosys/),
[espresso](https://github.com/chipsalliance/espresso),
[slang](https://github.com/MikePopoloski/slang),
and [filecheck](https://llvm.org/docs/CommandGuide/FileCheck.html).
Check that each is installed on your `PATH` by running `which verilator` and so on.
检查你是否安装有这些工具：verilator, yosys, espresso, slang 和 filecheck。通过运行 `which verilator` 等命令，你可以检查这些工具是否安装在 `PATH` 上。
If the compilation succeeded and the dependencies noted above are installed, you can then run the included unit tests by invoking:
如果编译成功并且上述依赖项已安装，则可以通过运行以下命令运行包含的单元测试：
```bash
./mill chisel[].test
```
### Running Projects Against Local Chisel // 运行项目对本地 Chisel
To use the development version of Chisel (`main` branch), you will need to build from source and publish locally.
The repository version can be found by running `./mill show unipublish.publishVersion`.
为了使用开发版本的 Chisel，你需要从源代码构建并发布到本地。仓库版本可以通过运行 `./mill show unipublish.publishVersion` 获得。
As of the time of writing it was: `7.0.0-M2+431-4798bea7-SNAPSHOT`
编写时间为：7.0.0-M2+431-4798bea7-SNAPSHOT
To publish your version of Chisel to the local Ivy repository, run:
为了将您的 Chisel 版本发布到本地 Ivy 仓库，请运行：
```bash
./mill unipublish.publishLocal
```
The compiled version gets placed in `~/.ivy2/local/org.chipsalliance/`.
编译的版本被放置在 `~/.ivy2/local/org.chipsalliance/`
If you need to un-publish your local copy of Chisel, remove the directory generated in `~/.ivy2/local/org.chipsalliance/`.
如果你需要取消发布 Chisel 的本地副本，请删除 `~/.ivy2/local/org.chipsalliance/` 生成的目录。
In order to have your projects use this version of Chisel, you should update the `libraryDependencies` setting in your project's build.sbt file to use the current version, for example:
为了使项目使用此版本的 Chisel，你需要更新项目的 build.sbt 文件中的 `libraryDependencies` 设置，例如：
```scala
val chiselVersion = "7.0.0-M2+431-4798bea7-SNAPSHOT"
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
```
### Chisel Architecture Overview // Chisel 架构概述
The Chisel compiler consists of these main parts:
Chisel 编译器由这些主要部分组成：
* **The frontend**, `chisel3.*`, which is the publicly visible "API" of Chisel and what is used in Chisel RTL. These just add data to the...
前端，`chisel3.*`，是 Chisel 公开的 "API"，这是在 Chisel RTL 中使用的。这些只是添加数据到...
* **The Builder**, `chisel3.internal.Builder`, which maintains global state (like the currently open Module) and contains commands, generating...
构造器，`chisel3.internal.Builder`，它维护全局状态（如当前打开的 Module）并包含命令，生成...
* **The intermediate data structures**, `chisel3.firrtl.*`, which are syntactically very similar to Firrtl. Once the entire circuit has been elaborated, the top-level object (a `Circuit`) is then passed to...
中间数据结构，`chisel3.firrtl.*`，与 Firrtl 语法非常相似。一旦整个电路被展开，顶层对象（一个 `Circuit`）将被传递给...
* **The Firrtl emitter**, `chisel3.firrtl.Emitter`, which turns the intermediate data structures into a string that can be written out into a Firrtl file for further processing.
Firrtl 转换器，`chisel3.firrtl.Emitter`，将中间数据结构转换为字符串，该字符串可以写入 Firrtl 文件以进行进一步处理。
Also included is:
还包含：
* **The standard library** of circuit generators, `chisel3.util.*`. These contain commonly used interfaces and constructors (like `Decoupled`, which wraps a signal with a ready-valid pair) as well as fully parameterizable circuit generators (like arbiters and multiplexors).
标准库，电路生成器，`chisel3.util.*`。这些包含 commonly used 接口和构造函数（如 `Decoupled`，它将信号包装成 ready-valid 对）以及全参数化的电路生成器（如仲裁者和多路选择器）。
* **Chisel Stage**, `chisel3.stage.*`, which contains compilation and test functions that are invoked in the standard Verilog generation and simulation testing infrastructure. These can also be used as part of custom flows.
chisel状态，`chisel3.stage.*`，包含编译和测试函数，它们在标准 Verilog 生成和仿真测试基础设施中调用。这些也可以作为自定义流程的一部分使用。
### Chisel Sub-Projects // Chisel 子项目
Chisel consists of several Scala projects; each is its own separate compilation unit:
Chisel 由一些 Scala 项目组成；每个都是自己的单独编译单元：
* [`core`](core) is the bulk of the source code of Chisel, depends on `firrtl`, `svsim`, and `macros`
core 是 Chisel 的 bulk 源代码，依赖于 firrtl、svsim 和 macros
* [`firrtl`](firrtl) is the vestigial remains of the old Scala FIRRTL compiler, much if it will likely be absorbed into `core`
firrtl 是 Scala FIRRTL 编译器的残余部分， 大多数被吸收到 core
* [`macros`](macros) is most of the macros used in Chisel, no internal dependencies
macros 是 Chisel 中使用的大多数宏，没有内部依赖
* [`plugin`](plugin) is the compiler plugin, no internal dependencies
plugin 是编译插件，没有内部依赖
* [`src/main`](src/main) is the "main" that brings it all together and includes a [`util`](src/main/scala/chisel3/util) library, which depends on `core`
src/main 是 "main"，将所有内容 together 并包含一个 [`util`](src/main/scala/chisel3/util) 库，该库依赖于 core
* [`svsim`](svsim) is a low-level library for compiling and controlling SystemVerilog simulations, currently targeting Verilator and VCS as backends
svsim 是一个用于编译和控制 SystemVerilog 仿真的底层库，目前目标后端为 Verilator 和 VCS
Code that touches lots of APIs that are private to the `chisel3` package should belong in `core`, while code that is pure Chisel should belong in `src/main`.
代码涉及 `chisel3` 包的私有 API 的大量 API，应该属于 `core`，而纯 Chisel 的代码应该属于 `src/main`。
### Which version should I use? // 哪个版本应该使用？
We encourage Chisel users (as opposed to Chisel developers), to use the latest release version of Chisel.
我们鼓励 Chisel 用户（而不是 Chisel 开发者），使用最新的发布版本 Chisel。
This [chisel-template](https://github.com/chipsalliance/chisel-template) repository is kept up-to-date, depending on the most recent version of Chisel.
这个 [chisel-template](https://github.com/chipsalliance/chisel-template) 存储库被更新，取决于最新的 Chisel 版本。
The recommended version is also captured near the top of this README, and in the [Github releases](https://github.com/chipsalliance/chisel/releases) section of this repo.
推荐版本可从本README文档头部获取到，并在此仓库的 [Github releases](https://github.com/chipsalliance/chisel/releases) 部分。
If you encounter an issue with a released version of Chisel, please file an issue on GitHub mentioning the Chisel version and provide a simple test case (if possible).
如果你遇到 Chisel 的某个版本问题，请将问题报告给 GitHub，并提及 Chisel 版本，并尽可能提供简单测试用例。
Try to reproduce the issue with the associated latest minor release (to verify that the issue hasn't been already addressed).
尝试使用关联的次要版本（以验证该问题是否已被处理）重新 reproduce 问题。
For more information on our versioning policy and what versions of the various Chisel ecosystem projects work together, see [Chisel Project Versioning](https://www.chisel-lang.org/chisel3/docs/appendix/versioning.html).
对于更多信息，有关我们的版本控制策略，以及哪些版本的 Chisel 生态系统项目一起工作，请查看 [Chisel 项目版本控制](https://www.chisel-lang.org/chisel3/docs/appendix/versioning.html)。
If you're developing a Chisel library (or `chisel3` itself), you'll probably want to work closer to the tip of the development trunk.
如果你正在开发 Chisel 库（或 `chisel3` 本身），你可能会想要与开发树的建议一起工作。
By default, the main branch of the chisel repository is configured to build and publish its version of the code as `+--SNAPSHOT`.
默认的，chisel仓库的主分支被配置为构建并发布其代码的版本为 `+--SNAPSHOT`。
Updated SNAPSHOTs are published on every push to main.
更新的 SNAPSHOT 每次推送到主分支时都会发布。
You are encouraged to do your development against the latest SNAPSHOT, but note that neither API nor ABI compatibility is guaranteed so your code may break at any time.
你被鼓励使用最新的 SNAPSHOT 进行开发，但请注意，API 和 ABI 不保证兼容性，因此你的代码可能会随时中断。
### Roadmap // 路线图
See [Roadmap](ROADMAP.md).
详见 [Roadmap](ROADMAP.md)。