diff --git "a/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/uart_tx.v" "b/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/uart_tx.v"
new file mode 100644
index 0000000000000000000000000000000000000000..8de522584246b74a5b8d80ca1434a4e7cf1066db
--- /dev/null
+++ "b/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/uart_tx.v"
@@ -0,0 +1,73 @@
+/*uart串口发送模块*/
+module uart_tx
+#(
+    parameter   UART_BPS    =   'd9600,
+    parameter   CLK_FREQ    =   'd50_000_000
+)
+(
+    input   wire            sys_clk     ,
+    input   wire            sys_rst_n   ,
+    input   wire    [7:0]   pi_data     ,
+    input   wire            pi_flag     ,
+    
+    output  reg             tx
+);
+
+parameter BAUD_CNT_MAX = CLK_FREQ / UART_BPS;
+
+reg             work_en     ;
+reg     [15:0]  baud_cnt    ;
+reg             bit_flag    ;
+reg     [3:0]   bit_cnt     ;
+
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        work_en <= 1'b0;
+    else    if(pi_flag == 1'b1)
+        work_en <= 1'b1;
+    else    if(bit_cnt == 4'd9 && bit_flag == 1'b1)
+        work_en <= 1'b0;
+        
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        baud_cnt <= 16'd0;
+    else    if(work_en == 1'b0 || baud_cnt == BAUD_CNT_MAX - 10)
+        baud_cnt <= 16'd0;
+    else    if(work_en == 1'b1)
+        baud_cnt <= baud_cnt + 1'b1;
+        
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        bit_flag <= 1'b0;
+    else    if(baud_cnt == 16'd1)
+        bit_flag <= 1'b1;
+    else
+        bit_flag <= 1'b0;
+        
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        bit_cnt <= 4'd0;
+    else    if(bit_cnt == 4'd9 && bit_flag == 1'b1)
+        bit_cnt <= 4'd0;
+    else    if(work_en == 1'b1 && bit_flag == 1'b1)
+        bit_cnt <= bit_cnt + 1'b1;
+        
+always@(posedge sys_clk or negedge sys_rst_n)
+    if(sys_rst_n == 1'b0)
+        tx <= 1'b1;
+    else    if(bit_flag == 1'b1)
+        case(bit_cnt)
+            0: tx <= 1'b0;
+            1: tx <= pi_data[0];
+            2: tx <= pi_data[1];
+            3: tx <= pi_data[2];
+            4: tx <= pi_data[3];
+            5: tx <= pi_data[4];
+            6: tx <= pi_data[5];
+            7: tx <= pi_data[6];
+            8: tx <= pi_data[7];
+            9: tx <= 1'b1;
+            default:tx <= 1'b1;
+        endcase
+        
+endmodule
\ No newline at end of file