From 9b733831000f6e8e0113c5db42047955163c5ca7 Mon Sep 17 00:00:00 2001 From: wkr <12568105+rkforever@user.noreply.gitee.com> Date: Sun, 12 Mar 2023 03:02:37 +0000 Subject: [PATCH] =?UTF-8?q?add=20=E9=9D=A2=E5=90=91=E5=8F=AF=E7=BC=96?= =?UTF-8?q?=E7=A8=8B=E6=95=B0=E6=8D=AE=E5=B9=B3=E9=9D=A2=E7=9A=84=E6=AE=B5?= =?UTF-8?q?=E8=B7=AF=E7=94=B1=E7=BD=91=E7=BB=9C=E9=81=A5=E6=B5=8B/fifo=5Fs?= =?UTF-8?q?um=5Fctrl.v.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../fifo_sum_ctrl.v" | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 "\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/fifo_sum_ctrl.v" diff --git "a/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/fifo_sum_ctrl.v" "b/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/fifo_sum_ctrl.v" new file mode 100644 index 0000000..1fed1f5 --- /dev/null +++ "b/\351\235\242\345\220\221\345\217\257\347\274\226\347\250\213\346\225\260\346\215\256\345\271\263\351\235\242\347\232\204\346\256\265\350\267\257\347\224\261\347\275\221\347\273\234\351\201\245\346\265\213/fifo_sum_ctrl.v" @@ -0,0 +1,135 @@ +/*该模块为FIFO求和控制模块*/ + +module fifo_sum_ctrl +( + input wire sys_clk , + input wire sys_rst_n , + input wire pi_flag , + input wire [7:0] pi_data , + + output reg po_flag , + output reg [7:0] po_data +); + +parameter CNT_COL_MAX = 8'd3 , + CNT_ROW_MAX = 8'd4 ; + +wire [7:0] dout_1 ; +wire [7:0] dout_2 ; + +reg [7:0] cnt_col ; +reg [7:0] cnt_row ; +reg wr_en_1 ; +reg [7:0] wr_data_1 ; +reg wr_en_2 ; +reg [7:0] wr_data_2 ; +reg rd_en ; +reg dout_flag ; +reg sum_flag ; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_col <= 8'd0; + else if(cnt_col == CNT_COL_MAX && pi_flag == 1'b1) + cnt_col <= 8'd0; + else if(pi_flag == 1'b1) + cnt_col <= cnt_col + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_row <= 8'd0; + else if(cnt_col == CNT_COL_MAX && cnt_row == CNT_ROW_MAX && pi_flag == 1'b1) + cnt_row <= 8'd0; + else if(cnt_col == CNT_COL_MAX && pi_flag == 1'b1) + cnt_row <= cnt_row + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_en_1 <= 1'b0; + else if(cnt_row == 8'd0 && pi_flag == 1'b1) + wr_en_1 <= 1'b1; + else + wr_en_1 <= dout_flag; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_data_1 <= 8'd0; + else if(cnt_row == 8'd0 && pi_flag ==1'b1) + wr_data_1 <= pi_data; + else if(dout_flag == 1'b1) + wr_data_1 <= dout_2; + else + wr_data_1 <= wr_data_1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_en_2 <= 1'b0; + else if(cnt_row >= 8'd1 && (cnt_row <= CNT_ROW_MAX - 1'b1) && pi_flag == 1'b1) + wr_en_2 <= 1'b1; + else + wr_en_2 <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_data_2 <= 8'd0; + else if(cnt_row >= 8'd1 && (cnt_row <= CNT_ROW_MAX - 1'b1) && pi_flag == 1'b1) + wr_data_2 <= pi_data; + else + wr_data_2 <= wr_data_2; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_en <= 1'b0; + else if(cnt_row >= 8'd2 && (cnt_row <= CNT_ROW_MAX) && pi_flag == 1'b1) + rd_en <= 1'b1; + else + rd_en <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + dout_flag <= 1'b0; + else if(wr_en_2 == 1'b1 && rd_en == 1'b1) + dout_flag <= 1'b1; + else + dout_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + sum_flag <= 1'b0; + else if(rd_en == 1'b1) + sum_flag <= 1'b1; + else + sum_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_data <= 8'd0; + else if(sum_flag == 1'b1) + po_data <= dout_1 + dout_2 + pi_data; + else + po_data <= po_data; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_flag <= 1'b0; + else + po_flag <= sum_flag; + +fifo fifo_inst_1 ( + .clock (sys_clk ), + .data (wr_data_1), + .rdreq (rd_en ), + .wrreq (wr_en_1 ), + .q (dout_1) + ); + +fifo fifo_inst_2 ( + .clock (sys_clk ), + .data (wr_data_2), + .rdreq (rd_en ), + .wrreq (wr_en_2 ), + .q (dout_2) + ); + + +endmodule \ No newline at end of file -- Gitee